When learning high-speed circuit design, you must know these things![Copy link]
01. Power supply layout and wiring related
digital circuits often require discontinuous current, so surge current will be generated for some high-speed devices. If the power supply line is very long, the presence of surge current will cause high-frequency noise, and this high-frequency noise will be introduced into other signals. In high-speed circuits, there must be parasitic inductance, parasitic resistance and parasitic capacitance, so the high-frequency noise will eventually couple into other circuits, and the presence of parasitic inductance will also cause the maximum surge current that the line can withstand to decrease, resulting in partial voltage drop, which may cause the circuit to be disabled. Therefore, it is particularly important to add bypass capacitors in front of digital devices. The larger the capacitance, the more limited its transmission energy is in terms of transmission rate, so generally a large capacitor and a small capacitor are combined to meet the full frequency range.
Avoid hot spots: Signal vias will generate voids in the power layer and the bottom layer. Therefore, improper placement of vias is likely to increase the current density in certain areas of the power or ground plane. These places where the current density increases are called hot spots.
Therefore, we must try our best to avoid this situation when setting vias, so as to avoid the plane being cut, which will eventually lead to EMC problems. Usually, the best way to avoid hot spots is to place vias in a mesh, so that the current density is uniform, the plane will not be isolated, the return path will not be too long, and there will be no EMC problems.
02.
When laying high-speed signal lines, the signal lines should be bent as little as possible. If the lines have to be bent, do not use sharp or right angles, but use obtuse angles.
When laying high-speed signal lines, we often use serpentine lines to achieve equal length. The same serpentine line is actually a kind of bending of the line. The line width, spacing, and bending method should be reasonably selected, and the spacing should meet the 4W/1.5W rule.
03. Signal proximity
If the distance between high-speed signal lines is too close, crosstalk is likely to occur. Sometimes, due to layout, board frame size and other reasons, the distance between high-speed signal lines exceeds our minimum required distance, then we can only increase the distance between high-speed signal lines as much as possible near the bottleneck. In fact, if there is enough space, try to increase the distance between two high-speed signal lines.
04 Routing stubs
A long stub line is equivalent to an antenna. Improper handling will cause serious EMC problems. At the same time, the stub line will also cause reflections, reducing the integrity of the signal. Usually, when adding pull-up or pull-down resistors on high-speed signal lines, stub lines are most likely to be generated. Generally, stub lines can be daisy-wired. According to experience, if the length of the stub line is greater than 1/10 of the wavelength, it can be used as an antenna, which will become a problem.
05 Impedance discontinuity
The impedance value of the trace generally depends on its line width and the distance between the trace and the reference plane. The wider the trace, the smaller its impedance. The same principle applies to the pads of some interface terminals and devices. When the pad of an interface terminal is connected to a high-speed signal line, if the pad is particularly large and the high-speed signal line is particularly narrow, the large pad has a small impedance, and the narrow trace must have a large impedance. In this case, impedance discontinuity will occur, and impedance discontinuity will cause signal reflection. Therefore, in order to solve this problem, a copper foil is placed under the large pad of the interface terminal or device, and the reference plane of the pad is placed on another layer, thereby increasing the impedance and making the impedance continuous.
Vias are another source of impedance discontinuity. To minimize this effect, unnecessary copper between inner layers and vias should be removed. This can actually be done during design using CAD tools or by contacting PCB fabrication specialists to remove unnecessary copper to ensure impedance continuity.
06 Differential signal
High-speed differential signal lines must be of equal width and spacing to achieve a specific differential impedance value. Therefore, try to ensure symmetry when laying differential signal lines.
It is forbidden to place vias or components in the differential line pairs. If vias or components are placed in the differential line pairs, EMC problems will occur and impedance discontinuity will also occur.
Sometimes, some high-speed differential signal lines need to be connected in series with coupling capacitors. The coupling capacitors also need to be arranged symmetrically, and the package of the coupling capacitors cannot be too large. It is recommended to use 0402, 0603 is also acceptable, and capacitors above 0805 or parallel capacitors are best not to be used.
Typically, vias create large impedance discontinuities, so for high-speed differential signal pairs, minimize the number of vias and, if you must use vias, arrange them symmetrically.
07 Equal length
In some high-speed signal interfaces, such as buses, the arrival time and skew error between the signal lines need to be considered. For example, the arrival time of all data signal lines in a set of high-speed parallel buses must be guaranteed to be within a certain skew error to ensure the consistency of their setup time and hold time. In order to meet this requirement, we must consider equal length. The
high-speed differential signal line must ensure strict skew between the two signal lines, otherwise there is a high probability of communication failure. Therefore, in order to meet this requirement, serpentine lines can be used to achieve equal length and thus meet the skew requirement.
The serpentine line should generally be arranged at the source of the loss of length, rather than at the far end. Only at the source can the positive and negative signals of the differential line be transmitted synchronously most of the time.
If there are two bends in the traces and the distance between them is less than 15mm, the length loss of the two traces will compensate for each other, so there is no need to perform equal length processing.
For different parts of high-speed differential signal lines, they should be of equal length. Vias, series coupling capacitors and interface terminals will divide high-speed differential signal lines into two parts, so special attention should be paid at this time. They must be of equal length. Because many EDA software only focuses on whether the entire routing is out of length during DRC.
For interfaces such as LVDS display devices, there will be several pairs of differential pairs at the same time, and the timing requirements between the differential pairs are generally very strict, and the skew requirements are very small. Therefore, for such differential signals, we generally require compensation within the same plane. This is because the signal transmission speeds of different layers are different.
When calculating the length of a trace, some EDA software will also include the trace inside the pad in the calculation. If length compensation is performed at this time, the actual result will be inaccurate. Therefore, special attention should be paid when using some EDA software.
Thanks to the host for sharing the knowledge points, which are very comprehensive. It's just right for systematic learning!
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Published on 2023-9-21 11:44
There are many conclusions. Many times, when wiring, there will always be unavoidable frustration and it cannot be perfect. At that time, it was really entangled.
When it comes to PCB routing, there are actually two things that novices need to do to get started. First, copy the templates of predecessors, which are similar to each other. Second, fly the wires everywhere to achieve balance.
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Thanks for sharing!
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