Transistor and MOS tube
The transistor is a current control device that uses the change of base current to control the change of collector current. There are two types of transistors: NPN transistor and PNP transistor. The symbols are as follows:
MOS tube is a voltage-controlled current device that uses the change of gate voltage to control the change of drain current. There are P-channel MOS tube (PMOS for short) and N-channel MOS tube (NMOS for short), and the symbols are as follows (here we only discuss the commonly used enhancement MOS tube):
Correct Application of Transistors and MOS Tubes
NPN transistor
It is suitable for the case where the emitter is connected to GND and the collector is connected to the load to VCC. As long as the base voltage is higher than the emitter voltage (here GND) by 0.7V, that is, the emitter junction is forward biased (VBE is positive), the NPN transistor can start to conduct. The base drives the NPN transistor to conduct with a high level (not conducting when the level is low); in addition to the current limiting resistor, the better design is to connect a pull-down resistor of 10-20k to GND.
The advantages are:
When the base control level changes from high to low, the base can be pulled down faster, andthe NPN transistor can be cut off faster and more reliably.
When the system is just powered on, the base is a certain low level
As shown below, on the left.
PNP transistor
It is suitable for the case where the emitter is connected to VCC and the collector is connected to the load to GND. As long as the base voltage is lower than the emitter voltage (here VCC) by 0.7V, that is, the emitter junction is reverse biased (VBE is negative), the PNP transistor can start to conduct. The base is driven by a low level to conduct the PNP transistor (not conducting when the high level is high); in addition to the current limiting resistor, the better design is to connect a pull-up resistor of 10-20k to VCC.
The advantages are:
When the base control level changes from low to high, the base can be pulled up faster, andthe PNP transistor can be cut off faster and more reliably.
When the system is just powered on, the base is a certain high level
As shown below, in the picture on the right.
So, as above:
For NPN transistors, the optimal design is that load R12 is connected between the collector and VCC. An inconsiderate design is that load R12 is connected between the emitter and GND.
For a PNP transistor, the optimal design is that the load R14 is connected between the collector and GND. An inconsiderate design is that the load R14 is connected between the emitter and VCC. In this way, the load change can be prevented from being coupled to the control terminal. This can be clearly seen from the direction of the current.
PMOS
It is suitable for the case where the source is connected to VCC and the drain is connected to the load to GND. As long as the gate voltage is lower than the source voltage (here VCC) by more than Vth (that is, Vgs exceeds -Vth), the PMOS can start to conduct. The gate drives the PMOS to conduct with a low level (not conducting when the gate is high); in addition to the current limiting resistor, the better design is to connect a pull-up resistor of 10-20k to VCC, so that when the gate control level changes from low to high, the gate can be pulled up faster, and the PMOS can be cut off faster and more reliably.
NMOS
It is suitable for the case where the source is connected to GND and the drain is connected to the load to VCC. As long as the gate voltage is higher than the source voltage (here GND) and exceeds Vth (that is, Vgs exceeds Vth), NMOS can start to conduct. The gate drives NMOS to conduct with a high level (not conducting when the level is low); in addition to the current limiting resistor, the better design is to connect a pull-down resistor of 10-20k to GND, so that when the gate control level changes from high to low, the gate can be pulled down faster, and NMOS can be turned off faster and more reliably .
So, as above:
For PMOS, the optimal design is that the load R16 is connected between the drain and GND. The less thoughtful design is that the load R16 is connected between the source and VCC.
For NMOS, the optimal design is that the load R18 is connected between the drain and VCC. The less thoughtful design is that the load R18 is connected between the source and GND.
Summarize
To prevent changes in the load from being coupled to the control terminal (base Ib or gate Vgs) of precision logic devices (such as MCU), the load should be connected to the collector or drain.
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