Analysis of some situations of MOS tube "breakdown"

What is the breakdown of MOSFET? Are you serious? What are the breakdowns of MOSFET? Do you understand it? Today I will give you some knowledge about the breakdown of MOSFET! Come and learn~ The breakdown of MOSFET It is divided into three types: Source, Drain, and Gate. The three poles of the field effect transistor: source S, drain D, and gate G. (We do not talk about the breakdown of the gate GOX here, but only the breakdown of the drain voltage).

Let’s talk about the test conditions first. The source and gate substrates are all grounded, and then the drain voltage is scanned until the Drain terminal current reaches 1uA. So from the perspective of the device structure, there are three leakage channels: Drain to source, Drain to Bulk, and Drain to Gate.

1.Drain→Bulk avalanche breakdown

This is simply avalanche breakdown of the PN junction (**alanche Breakdown). The main reason is that the depletion region of the PN junction is widened under the reverse bias voltage of the drain, and the reverse bias electric field is added to the reverse bias of the PN junction, causing electrons to accelerate and impact. The crystal lattice generates new electron-hole pairs, and then the electrons continue to collide. This avalanche multiplies and leads to breakdown. Therefore, the current of this breakdown increases almost rapidly, and the IV curve goes up almost vertically, making it easy to burn out. of. (This is different from source-drain punch-through breakdown)

So how to improve this juncTIon BV? So we mainly start from the characteristics of the PN junction itself. We must reduce the electric field in the depletion region to prevent collisions from generating electron-hole pairs. Lowering the voltage will definitely not work, so we can only increase the width of the depletion region. , so the doping profile needs to be changed. This is why the breakdown voltage of the abrupt junction (Abrupt junction) is lower than that of the graded junction (Graded Junction). This is to apply what you have learned and follow what others have said.

Of course, in addition to the doping profile, there is also the doping concentration. The greater the concentration, the narrower the width of the depletion region, so the stronger the electric field intensity, which will definitely reduce the breakdown voltage. And there is another rule that the breakdown voltage is usually more affected by the concentration on the low concentration side because the depletion region width there is large. The formula is BV=K*(1/Na+1/Nb). It can also be seen from the formula that if the concentration of Na and Nb differs by 10 times, almost one of them can be ignored. If the actual process finds that the BV becomes smaller and it is confirmed to be from the junction, then check your Source/Drain implant.

2.Drain→Source penetration breakdown

This is mainly due to the application of a reverse bias voltage to Drain, which causes the depletion region of the PN junction of Drain/Bulk to extend. When the depletion region touches the Source, the source and drain do not need to be opened to form a path, so it is called punch-through ( punch through). So how to prevent punch-through? This goes back to the reverse bias characteristics of the diode. In addition to the voltage, the width of the depletion region is also related to the doping concentration on both sides. The higher the concentration, the higher the concentration can suppress the extension of the depletion region width, so there is An anti-punch through injection (APT: AnTI Punch Through), remember that it needs to be of the same type as well. Of course, when you actually encounter WAT BV running and it must be running from the Source side, it may also depend on whether it is PolyCD or Spacer width, or LDD_IMP problem, so how to eliminate it? It depends on whether you have both NMOS and PMOS running. ?POLY CD can be verified through Poly related WAT.

For punch-through breakdown, there are some characteristics:

(1) The breakdown point of punch-through breakdown is soft, and during the breakdown process, the current gradually increases. This is because the depletion layer expands wider and generates a larger current. On the other hand, the DIBL effect is prone to occur when the depletion layer is widened, causing the forward bias of the source substrate junction to gradually increase the current.

(2) The soft breakdown point of punch-through breakdown occurs when the depletion layers of the source and drain are connected. At this time, the carriers at the source end are injected into the depletion layer and are accelerated by the electric field in the depletion layer to reach the drain end. Therefore, , the current of punch-through breakdown also has a sharp increase point. This sharp increase of current is different from the sharp increase of current during avalanche breakdown. The current at this time is equivalent to the current when the PN junction of the source substrate is forwardly conductive, while avalanche breakdown The current is mainly the avalanche current when the PN junction reversely breaks down. If the current is not limited, the avalanche breakdown current will be larger.

(3) Punch-through breakdown generally does not cause destructive breakdown. Because the punch-through breakdown field strength does not reach the field strength of avalanche breakdown, a large number of electron-hole pairs will not be generated.

(4) Punch-through breakdown generally occurs in the channel body, and punch-through is not easy to occur on the channel surface. This is mainly caused by the channel injection making the surface concentration larger than the concentration. Therefore, NMOS tubes generally have punch-through injection prevention.

(5) Generally, the concentration at the edge of the beak is greater than the concentration in the middle of the channel, so punch-through breakdown generally occurs in the middle of the channel.

(6) The length of the polycrystalline gate has an impact on punch-through breakdown. As the gate length increases, the breakdown increases. Strictly speaking, it also has an impact on avalanche breakdown, but it is not that significant.

3.Drain→Gate breakdown

This is mainly gate oxide breakdown caused by the overlap between Drain and Gate. This is a bit similar to GOX breakdown. Of course, it is more like Poly finger's GOX breakdown, so it may be more careful about poly profile and sidewall damage. . Of course, another problem with this Overlap is GIDL, which will also contribute leakage and reduce BV.

The above are the three channels of MOSFET breakdown. Usually there are two cases of BV, which are breakdown in Off-state, that is, when the Gate is 0V, but sometimes when the Gate is turned on and Drain is applied, the voltage is applied. Too high will also lead to breakdown, which we call On-state breakdown. This situation especially likes to occur when the Gate voltage is low, or when the tube has just been turned on, and it is almost always NMOS. So we usually also test BVON with WAT.

Don't think it's strange, but you must pay attention when testing the condition. The voltage on Gate is not arbitrarily applied. It must be a voltage near Vt. The lower the Vg, the lower the on-state breakdown is. It may be caused by Snap-back, but the test machine limitation cannot test the standard snap-back curve. In addition, it is also possible that the current density at the moment of turning on is too high, causing a large number of electrons to be accelerated and impacted by the depletion zone electric field near the PN junction. The above is the breakdown of MOSFET, I hope it can help you.