LTC2323-12 chip does not work

1152147636

LTC2323-12 chip does not work [Copy link]

The chip uses LVDS standard to output data and applies internal reference voltage. The chip is powered normally and the measured results are:

1. REFOUT1 (Pin 12) and REFOUT2 (Pin 26) pin voltage 4.096V;

2. VBYP1 (Pin 13) and VBYP2 (Pin 24) pin voltage 1.6V ;

3. VDD power supply 5V, OVDD power supply 2.5V;

4. CMOS /LVDS (Pin 25) directly connected to OVDD;

5. REFINT (Pin 28) is directly connected to VDD;

6. For the timing of CNV (Pin 9) and SCK + , SCK – (Pins 21, 22), only the falling time of the CNV falling edge exceeds 1ns, which does not meet the requirement. The actual falling time is about 3ns.

Currently the chip does not work properly: CLKOUT + , CLKOUT – (Pins 17, 18), SDO1 + , SDO1 – (Pins 15, 16), SDO2 + , SDO2 – (Pins 19, 20) have no output

I personally suspect that the chip cannot work properly because the falling time of the CNV falling edge exceeds 1ns. I don't know if this is the case. Please help me solve this problem if you have used this AD chip. Thank you!

Jacktang

Normal power supply does not necessarily mean normal operation

The falling time of CNV falling edge exceeds 1ns

What is the reason for suspicion?

littleshrimp

The falling edge of CNV should not affect the data output. The normal clock can be lower, no more than 5MHz. The reference voltage output indicates that the analog part is working properly. You should focus on checking the circuit of the digital part, such as whether OVDD is well soldered, and whether the CNV and SCK signal inputs are normal. Note that CNV is CMOS level, SCK is LVDS level, and then compare the SCK and CLKOUT signals to determine whether the digital part of the chip is working properly.

littleshrimp

If the CMOS/LVDS circuit is not fixed, try using CMOS mode to see if there is any output, and what method did you use to measure the output? Directly using an oscilloscope or using the logic analyzer inside the FPGA?