[Perf-V Evaluation] Clock generation based on Perf-V development board

superstar_gu

[Perf-V Evaluation] Clock generation based on Perf-V development board [Copy link]

1. Introduction

This article is based on the Perf-V development board and uses the technology provided by Xilinx to generate clock signals of multiple frequencies according to the given frequency signal, which is used to generate clocks of different levels.

Xilinx FPGA devices have dedicated hardware resources inside to support the use of a large number of design clocks. The Perf-V board has an active crystal oscillator that generates a 50M clock signal and enters the device through the input port SYS_CLK (N14).

The external clock can be generated by other clocks through MMCM, PLL, BUFR, etc., or it can be converted by conventional units such as LUT and register (usually called gated clock).

2. Master clock

The master clock usually comes from two sources:
(1) the board-level clock entering the design through the input port;
(2) the output pin of the GT transceiver (such as the recovered clock).

The master clock must be connected to a netlist object that represents the starting point for all clock edges and propagates down the clock tree.

The primary clock can only be defined by the create_clock command and must be placed at the beginning of the constraint, because other timing constraints almost all refer to the primary clock. This article sets SYS_CLK (N14) as the primary clock as shown below:

create_clock -period 20 -name clk_in1 [get_ports clk_in1];

3. Generated Clock

A generated clock is a clock driven by logic in a design's internal units (such as MMCM, PLL, etc.). A generated clock is related to a parent clock. The parent clock can be a master clock or another generated clock.

We can configure the clock Clocking Wizard in the IP core to achieve this.

(1) Change the input clock mode to PLL, the frequency is 50MHz

(2) Change the frequency of the output clock of several channels

Click "Finish" to generate the following top-level file

`timescale 1ps/1ps

(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=2,clkin1_period=20.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)

module clk_wiz_0 
 (
  // Clock out ports
  output        clk_out1,
  output        clk_out2,
  // Status and control signals
  input         reset,
  output        locked,
 // Clock in ports
  input         clk_in1
 );

  clk_wiz_0_clk_wiz inst
  (
  // Clock out ports  
  .clk_out1(clk_out1),
  .clk_out2(clk_out2),
  // Status and control signals               
  .reset(reset), 
  .locked(locked),
 // Clock in ports
  .clk_in1(clk_in1)
  );

endmodule

Perform behavioral level simulation on the newly generated IP. The code is as follows

`timescale 1ns / 1ps
module sim_clk_wiz_0(

    );
    // Clock out ports
      wire        clk_out1;
      wire        clk_out2;
      // Status and control signals
      reg         reset;
      wire        locked;
     // Clock in ports
      reg         clk_in1;
      
      clk_wiz_0 clk_wiz_0_sim(
      // Clock out ports
        .clk_out1(clk_out1),
        .clk_out2(clk_out2),
        // Status and control signals
        .reset(reset),
        .locked(locked),
       // Clock in ports
        .clk_in1(clk_in1)
      );
      initial
          begin
              clk_in1 = 0;
              #100;
              reset = 1;
              #100;
              reset = 0;
          end
      always #10 clk_in1 = ~clk_in1;
      
endmodule

The simulation results are as follows:

4. Generate through constraints

The generated clock is defined using the create_generated_clock command. This command does not set the period or waveform, but describes how the clock circuit converts the parent clock. This conversion can be the following relationship:

(1) Simple frequency division
(2) Simple frequency multiplication
(3) Combination of frequency multiplication and division to obtain a non-integer ratio, usually performed by MMCM or PLL
(4) Phase shift or waveform inversion
(5) Duty cycle change
(6) Combination of all the above

For example, a 100M clock can be obtained by dividing by 2, as shown in the following code:

create_generated_clock -name clkdiv2 -source [get_ports clk_in1] -divide_by 2 [get_pins REGA/Q];

Jacktang

Is the external 50M clock signal and the generated clock understood as the online clock relationship?

Jacktang

What does behavioral simulation mean and how does it relate to clock generation?

superstar_gu

Jacktang posted on 2021-3-12 23:03 What does behavioral simulation mean and how does it relate to clock generation

Generating a clock is to use the internal circuit of the FPGA to build a circuit, and the resulting clock