Hardware structure of TMS320C55x

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Hardware structure of TMS320C55x [Copy link]

1.1C55x CPU system

C55x has one 32-bit program data bus (PB), five 16-bit data buses (BB, CB, DB, EB, FB), one 24-bit program address bus and five 23-bit data address buses, which are connected to the CPU respectively. The bus is connected to the external program bus and data bus through the memory interface unit (M) to enable the CPU to access the external memory. This parallel multi-bus structure enables the CPU to complete one 32-bit program code read, three 16-bit data reads and two 16-bit data writes in one CPU cycle. C55x divides the CPU into four units according to different functions, namely the instruction buffer unit (I), the program flow unit (P), the address flow unit (A) and the data calculation unit (D).

The 24-bit program code address is transmitted on the read program address bus (PAB), and the 32-bit program code is sent to the instruction buffer unit I for decoding by the read program data bus (PB). The
three read data address buses (BAB, CAB, DAB) are used in conjunction with the three read data buses (BB, CB, DB), that is, BAB corresponds to BB, CAB corresponds to CB, and DAB corresponds to DB. The address bus specifies the data space or I/O space address, and transmits 16-bit data to each functional unit of the CPU through the data bus. Among them, BB is only connected to the D unit to realize data transfer from the memory to the D unit multiplier accumulator (MAC). Special instructions can also use BB, DB and CB to read three operands at the same time.
Two write data address buses (EAB, FAB) are used in conjunction with two write data buses (EB, FB), that is, EAB corresponds to EB and FAB corresponds to FB. The address bus specifies the data space or I/O space address, and the data is transferred from the CPU's functional unit to the data space or I/O space through the data bus. All data space addresses are generated by the A unit. EB and FB receive data from the P unit, A unit, and D unit. For instructions that write two 16-bit data to the memory at the same time, EB and FB are used, while for instructions that complete a single write operation, only EB is used.
1.2 Instruction Buffer Unit (I unit)
The instruction buffer unit of C55x consists of the instruction buffer queue IBQ (Instruction Buffer Queue) and the instruction decoder. In each CPU cycle, the I unit puts the 4B program code received from the read program data bus into the instruction buffer queue. The instruction decoder takes 6B program code from the queue and decodes 8-bit, 16-bit, 24-bit, 32-bit and 48-bit variable-length instructions according to the length of the instruction. Then the decoded data is sent to the P unit, A unit and D unit for execution. The IBQ can store up to 64b of instructions to be decoded.
1.3 Program flow unit (P unit)

The program flow unit consists of a program address generation circuit and a register group. The program flow unit generates the addresses of all program spaces and controls the order in which instructions are read.
The task of the program address generation logic circuit is to generate a 24-bit address for reading the program space. Generally, it generates a continuous address. If the instruction requires reading the program code of a non-continuous address, the program address generation logic circuit can receive the immediate value from the I unit and the register value from the D unit, and transmit the generated address to the PAB.
The registers used in the P unit are divided into five types.
(1) Program flow registers: including the program counter (PC), the return address register (RETA) and the control flow relationship register (CFCT).
(2) Block repeat registers: including block repeat registers 0 and 1 (BRC0, BRC1), the storage register of BRC1 (BRS1), the block repeat start address registers 0 and 1 (RSA0, RSA1) and the block repeat end address registers 0 and 1 (REA0, REA1).
(3) Single repeat register: including single repeat counter (RPTC) and calculation single repeat register (CSR).
(4) Interrupt register: including interrupt flag register 0 and 1 (IFR0, IFR1), interrupt enable register 0 and 1 (IER0, IER1) and debug interrupt enable register 0 and 1 (DBIER0, DBIER1);
(5) Status register: including status register 0, 1, 2 and 3 (ST0-55, ST1-55, ST2-55 and ST3-55).
1.4 Address flow unit (A unit)
The address flow unit consists of data address generation circuit (DAGEN), arithmetic logic circuit (ALU) and register group.
The data address generation circuit (DAGEN) can receive the immediate value from the I unit and the register from the A unit to generate the address of the read data space. For instructions using indirect addressing mode, the P unit tells DAGEN the addressing mode to use.
The A unit includes a 16-bit arithmetic logic circuit (ALU), which can receive immediate data from the I unit and communicate with the memory, I/O space, A unit register, D unit register and P unit register in both directions. The ALU can perform arithmetic operations, logical operations, bit operations, shifts, tests and other operations.
The A unit includes the following types of registers.
(1) Data page registers: including data page registers (DPH, DP) and interface data page registers (PDP);
(2) Pointers: including coefficient data pointer registers (CDPH, CDP), stack pointer registers (SPH, SP, SSP) and 8 auxiliary registers (XAR0 ~ XAR7);
(3) Circular buffer registers: including circular buffer size registers (BK03, BK47, BKC), circular buffer start address registers (BSA01, BSA23, BSA45, BSA67, BSAC);
(4) Temporary registers: including temporary registers (T0 ~ T3).
1.5 Data calculation unit (D)
The data calculation unit consists of a shifter, an arithmetic logic circuit, a multiplier accumulator and a register group. The D unit contains the main computing components of the CPU.
The D unit shifter can receive immediate data from the I unit and can communicate bidirectionally with memory, I/O space, A unit registers, D unit registers, and P unit registers. In addition, it can provide shifted data to the D unit ALU and the A unit ALU. The shifter can perform the following operations:
(1) It can shift the 40-bit accumulator to the left by up to 31 bits and to the right by up to 32 bits. The shift number can be read from the temporary register (T0 to T3) or provided by a constant in the instruction;
(2) It can shift the 16-bit register, memory, or I/O space data to the left by 31 bits or to the right by 32 bits;
(3) It can shift the 16-bit immediate data to the left by up to 15 bits.

The 40-bit arithmetic logic circuit of the D unit can perform the following operations:
(1) perform addition, subtraction, comparison, Boolean logic operations, and absolute value operations;
(2) can perform two arithmetic operations simultaneously when executing a dual 16-bit arithmetic instruction;
(3) can set and clear bits of the D unit registers.