TMS320C55x instruction set

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TMS320C55x instruction set [Copy link]

C55x accesses data space, memory mapped registers, register bits, and I/O space through the following three addressing modes:

Absolute addressing mode Addressing
is accomplished by specifying a constant address in the instruction

Direct addressing mode Addressing
using address offset

Indirect addressing mode
Addressing is accomplished using pointers
1. Absolute addressing mode
C55x has absolute addressing mode:

1.1 k16 absolute addressing
The operand is *abs16(#k16), [k16: 16-bit unsigned constant]
The 7-bit register DPH and k16 are cascaded to form a 23-bit address for accessing the data space.

1.2
The operand of k23 absolute addressing is *(#k23), [k23: 23-bit unsigned constant]
1.3
The operand of I/O absolute addressing is *port(#k16), [k16: 16-bit unsigned constant]
Using the mnemonic instruction, its operand is port(#k16) (there is no * before the operand)

2. Direct addressing mode
Note: DP and SP are mutually exclusive and are selected by the CPL bit of ST1_55. 0 DP, 1 SP,

2.1 DP direct addressing

The upper 7 bits are provided by DPH and are used to determine the main data page

The lower 16 bits consist of two parts:

DP

7-bit offset (Doffset)

2.2 SP direct addressing

SPH determines the high 7 bits of the address

The 16-bit address is determined by SP and a 7-bit offset, and the offset range is 0~127

The extended data stack pointer XSP is composed of SPH and SP

2.3 Register Bit Addressing

The operand is @bitoffset.
Only register bit test, set, clear, and invert instructions support this addressing mode.
2.4 PDP direct addressing

port() specifies that the I/O space is accessed instead of the data storage unit.

3. Indirect addressing mode
3.1 AR indirect addressing

Access the data space through an auxiliary register ARn (n=0,1,2,3,4,5,6,7)
The ARMS bit of ST2-55 determines the operation type of AR indirect addressing
ARMS=0, DSP mode: CPU provides efficient execution function for DSP enhanced applications
ARMS=1, control mode: CPU can optimize the code length
3.2 Dual AR indirect addressing

Access two data storage units simultaneously through 8 auxiliary registers (AR0~AR7)
Function:
Execute one instruction to complete two 16-bit data space accesses
Execute two instructions in
parallel 3.3 CDP indirect addressing

Use the coefficient data pointer (CDP) to access data space, register bits, and I/O space
3.4 Coefficient indirect addressing

The following arithmetic instructions are supported:
FIR filter
Multiplication
Multiply-add
Multiply-subtract
Dual multiply-add or dual multiply-subtract

instruction system1
Parallel execution

Characteristics of instruction parallelism

Built-in parallelism in a single instruction - implicit parallelism
For example: MPY *AR0, *CDP, AC0
::MPY *AR1, *CDP, AC1
User-defined parallelism between two instructions
For example: MPYM *AR1–, *CDP, AC1
|| XOR AR2, T1
Built-in and user-defined mixed parallelism
For example: MPYM T3=*AR3+, AC1, AC2
|| MOV #5, AR1
Rules for instruction parallelism
The total length of the two instructions cannot exceed 6 bytes
There is no conflict in the operation unit, address generation unit, bus and other resources during the execution of the instructions
One of the instructions must have a parallel enable bit or the two instructions meet the soft-dual parallel conditions
Situations where parallelism cannot be used
Use immediate addressing mode
For example: *abs16(#k16);*(#k23);port(#k16); *ARn(K16);*+ARn(K16);*CDP(K16); *+CDP(K16)
Conditional jump, conditional call, interrupt, reset and other program control instructions
For example: BCC P24, cond; CALLCC P24, cond; IDLE; INTR k5; RESET; TRAP k5
Use the following instructions or operation modifiers
For example: mmap(); port(); <instruction>.CR; <instruction>.LR
Resource Conflict Resource Arithmetic Unit
of C55x Operators used are: ALU of D unit, shifter of D unit, switch of D unit, switch of A unit, ALU of A unit and address generation unit of P unit Two data address (DA) generation units, one coefficient address (CA) generation unit and one stack address (SA) generation unit Only a given number of data address generation unit buses can be used Two data read (DR) buses, one coefficient read (CA) bus, two data write (DW) buses, 1 ACB bus (transfers the contents of D unit registers to operators of A unit and P unit), one KAB bus (immediate bus) and one KDB bus (immediate bus) Only a given number of buses can be used Soft-dual parallel conditions Two memory operands must be dual AR Indirect addressing mode instructions cannot contain high_byte (Smem) and low_byte (Smem) Instructions cannot read and write the same memory unit If the value of k4 in the instruction is 0~8, it will change XDP Therefore, it cannot form a parallel instruction with the instruction that loads DP. The read repeat count register (RPTC) instruction cannot form a parallel instruction with any of the following single repeat instructions. 2 The C55x instruction set can be divided into 6 types according to the operation type:

Note: The attributes of an instruction include: instruction, operation performed, whether there is a parallel enable bit, length, cycle, execution stage in the pipeline, and functional unit of execution.
Arithmetic operation instructions
Bit operation instructions
Extended auxiliary register operation instructions
Logical operation instructions
Move instructions
Program control instructions