Interrupt controller of C6678 developed by DSP

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Interrupt controller of C6678 developed by DSP [Copy link]

It is divided into two layers. One layer is the interrupt controller inside each core, which is called interrupt controller, abbreviated as intc; the other layer is for the entire chip, which is chip-level and outside each core. This is called chip-level interrupt controller, abbreviated as CIC.

In fact, the two layers have different functions. There is no need to elaborate on this. Intc can directly handle some interrupts, which are the same for each core, but there are some interrupts that cannot be seen by all cores if necessary. At this time, unified management is required outside all cores, which is CIC. On C6678, CIC can map interrupts. This function can map some interrupts to the core you want to take over, so that other cores cannot perceive the interrupt. For C6678, CIC can control up to 1024 interrupts in total. The control method is to map each interrupt to one of the 256 channels through configuration. Multiple interrupts can be mapped to one channel at the same time. The interrupts mapped to the same channel are logically "or" with each other, that is, if any of the interrupts occurs, the channel will report the interrupt; after the system events are mapped to the channel, the interrupt reporting cannot be completed. These 256 channels need to be mapped to the host interrupt, and the maximum number of host interrupts is also 256. The host interrupt number corresponds to CICx_OUTn one by one, but the entire correspondence is not numbered from CIC0 to the last CICx, but CIC is divided into multiple, and the OUT of each CIC is numbered starting from OUT0. In fact, the input from CICx_OUTn to the intc of corepac is fixed, as shown below:

For example ,
in line 21, for core0, the system event 21 of core0's intc is connected to CIC0_OUT (32 + 0 + 11 * 0), that is, CIC0_OUT32. It is impossible for other cores to take over CIC0_OUT32.

Similarly, for core1, the system event 21 of core1 intc is connected to CIC0_OUT (32 + 0 + 11 * 1), that is, CIC0_OUT43. This CIC0_OUT43 can only be taken over by core1, and it is impossible for other cores to take over CIC0_OUT43. The same goes for other cores.

Therefore, for the entire process from CIC input to the final core processing, there are three links to determine which core will process the CIC input. These three links are:

1. Mapping of system interrupt to channel

2. Channel to host interrupt map

3. Connection from host interrupt to corepac intc

The reason why the last one is called connection instead of map is that there is no such thing as map or no map at this level, but it is directly connected, as shown in the analysis below the figure above. Among the previous two maps, only one can be truly considered a map, which is the first one, the map from system interrupt to channel, because this level is configurable and can be configured at will, and the second map, that is, the map from channel to host interrupt, is actually fixed by hardware, but there is a map status register that can be queried. The third one is also fixed by hardware, and seems to be similar to the second one, but it is not called a map. The reason is that at this level, there is not even a mapping query like the second level.

Therefore, if the system interrupt needs to be configured so that the core to be processed can correctly perceive it, it is mainly necessary to configure level 1, that is, the map of system interrupt to channel, and the configuration of level 1 needs to be determined according to the relationship between level 2 and level 3. For example, if there is an interrupt connected to CIC, if we want this interrupt to be taken over by core0, then first confirm that core0 can respond to those CICx_OUTn, and then confirm the host interrupt number of this OUTn. At this time, we can confirm which channel is mapped to the host interrupt, and then map the CIC interrupt to be taken over by core0 to the corresponding channel. Finally, several enables are required, including the enable of CIC input, the enable of host interrupt, and the enable of event corresponding to intc. Of course, not all interrupts on CIC can be taken over by core0, because the interrupts that can be mapped to core0 are actually limited to those on CIC0. The specific restrictions are shown in the figure below:

宋元浩

Thanks for sharing