Analysis of the Design Method of DSP and Slow Peripheral Device Interface

fish001

Analysis of the Design Method of DSP and Slow Peripheral Device Interface [Copy link]

Compared with conventional single-chip microcomputers, the internal structure and timing of DSP have changed greatly. Therefore, the interface chip suitable for single-chip microcomputers may not be suitable for DSP. For designers who are very familiar with single-chip microcomputer circuits, special attention should be paid to the selection of chips and the matching of timing when designing DSP circuits. In particular, when dealing with the interface between DSP and slow devices or devices, the correct timing matching is crucial.
　　In order to adapt to slower external memory and input/output devices, DSP is equipped with a software-programmable wait state generator, which can extend the external bus cycle to several machine cycles. Due to the limitation of hardware conditions, this extension is usually limited. For example, the DSP of the C54XX series can only be extended to 14 machine cycles at most, and the DSP of the C2XX series can only be extended to 7 machine cycles at most. However, in actual application, input/output devices with slower read and write cycles are often encountered, such as LCD display modules, printers, keyboards, etc. Therefore, it is impossible to achieve input/output timing matching by controlling the internal state wait generator only through software programming, and external hardware expansion design must be carried out.
　

　　In the process of designing the interface between DSP and slow peripheral devices, the dual CPU method is usually adopted. The DSP completes high-speed data processing and calculation, and the ordinary single-chip microcomputer (such as the 51 series single-chip microcomputer) realizes the input/output function of the system. This method increases the complexity of the system due to the use of two CPUs with different structures, and the interface and debugging are more difficult. This article will use the READY (external device ready) pin of the DSP to realize the automatic waiting of the external state through hardware expansion, so that the DSP and the slow input/output device can be directly connected to achieve the timing matching of access. This method is easy to interface, the hardware expansion circuit is not complicated, and the internal and external wait states are used in combination to generate any number of wait states. It is even possible to design the external hardware wait state as a controlled mode, and only start the external wait state when needed. In this way, it will be more flexible when used.
　　1 DSP I/O read and write timing
　　TMS320F206 DSP chip is now introduced as an example. Its clock frequency is set to 20MHz, and its external read and write timing is shown in Figure 1.
　　The read cycle of TMS320F206 is one clock cycle (5ns), and the write cycle is two clock cycles. The hold time T1 and T2 of the read and write operation data are only a few nanoseconds. The internal programmable wait state generator can only be extended to wait for 7 clock cycles at most, that is, 350ns. Using the internal state wait, only the read and write timing of the DSP and the peripheral chips of the commonly used single-chip microcomputer can be matched.
　

　　2 Read and write timing of slow devices
　　Now take the MDL (S) 16465 character LCD display module as an example. Its read and write timing is shown in Figure 2 and Figure 3. The
　　minimum read and write cycle Tcyc of the LCD module is 1000ns. The minimum pulse width Pw is 450ns, and the minimum read and write operation data retention time is 10ns. If the TMS320F206 is directly connected to the LCD module interface, even if the maximum number of state waits is used, the read and write timing of the DSP cannot meet the requirements of the LCD module. In order to achieve the timing matching between the two, this article will give a suitable external hardware wait expansion method to realize the direct read and write access control between the DSP and the LCD module.
　　3 DSP's READY signal
　　TMS320F206 provides two state wait options, one is the on-chip state wait product, which can realize limited programmable state wait; the other is the READY signal, which can be used for hardware expansion to generate any number of state waits from outside the chip.
　　When the DSP is performing external read and write operations, if the READY pin signal is low, the DSP will wait for one clock cycle and then check the READY signal again. Before the READY pin is driven to a high level, the program is in a waiting state and will not continue to execute. If the READY signal is not used, the READY should always remain at a high level during the DSP's external access.
　　By using the DSP's READY signal and related external access control signals, through hardware expansion, external automatic state waiting can be achieved, so that the DSP can directly connect and access slow external devices.
　　

　　4 Direct access interface between DSP and slow external devices The
　　external state waiting hardware expansion circuit is implemented by a 12-level binary ripple counter 74HC4040. The frequency of the output signal of each level of this chip is half of that of the previous level. The clock output signal CLKOUT1 of TMS320F206 is used as the input clock of 74HC4040. If CLKOUT1 is 20MHz, the maximum waiting time can reach 2 12×50ns. Users can select different output pins of 74HC4040 for waiting control according to the timing requirements of external devices. Due to the high frequency of the input clock, the response speed of general CD4040 or MC14040 chips is not fast enough. At least 74HC4040 or a chip with faster response speed should be selected. The
　　automatic hardware waiting expansion circuit is shown in Figure 4. The Q5 pin output of 74HC4040 is selected as the delay waiting control, and the waiting time is 1600ns. The Q4 pin output signal is ORed with the DSP's read and write signals to generate the external device's read and write control signals, which can fully guarantee the data retention time during read and write operations. The timing generated by this circuit is shown in Figure 5.
　　After the above hardware state waiting expansion, the DSP reaches an external device read and write cycle of 1600ns, and the data retention time of the read and write operation is greater than 20ns, which meets the timing requirements of the LCD module. In addition, when the DSP is accessing internal programs and data, READY is always at a high level, which does not affect the internal operating speed of the DSP. Using this circuit, the direct access connection between the DSP and the MDL (S) 16465 LCD module is shown in Figure 6.
　

　　RS is the data command control input terminal of the liquid crystal module, "1" indicates data, "0" indicates command; R/W is the read/write control input terminal, "1" indicates read operation, "0" indicates write operation; E is the enable control input terminal, high level is effective. According to the connection method in Figure 6, two address lines A8 and A9 are connected to RS and R/W respectively. According to the function definition of each pin, the command port write address of the liquid crystal module is 0000H, the command port read address is 0200H, the data port write address is 0100H, and the data port read address is 0300H. The access control subroutine of DSP to LCD module is as follows:
　　lcdcwaddr .set 0000h ;instruction port write address
　　lcdcraddr .set 0200h ;instruction port read address
　　lcddwaddr .set 0100h ;data port write address
　　lcddraddr .set 0300h ;data port read address
　　lcdenable:splk #6ff2h，60h ;io1=1
　　out 60h，iosr ;lcd enabled
　　ret
　　lcddisable:splk #6ff0h，60h ;io1=0
　　out 60h，iosr ;lcd disabled
　　lcdrw: call lcdenable
　　in 60h，［read address］ ；read operation
　　out 61h，［write address］ ；write operation
　　call lcddisable
　　ret
　　uses IO1 of TMS320F206 as the read/write enable control signal to call the two subroutines LCDENABLE and LCDDISABLE to open and close the access function to the LCD module. In addition to calling two simple control sub-functions, the read and write operations are completed by the two instructions IN and OUT respectively, realizing direct read and write access to the LCD module. Since the LCD module does not have a separate read/write control pin, the access control requirements are relatively special, so it can only be connected as shown in Figure 6.
　　

　　If the external device has a separate read and write control pin, it can be directly connected to DEV-RD and DEV-WE in Figure 4, and then the data line and the address line are connected accordingly, so that direct read and write access control can be performed. The author uses this connection method when processing keyboard input and printer output interfaces. The results show that both access and control are very reliable.
　　As the application of DSP becomes more and more extensive, as a complete control system and test equipment, basic input/output functions such as parameter equipment and result display are indispensable. Therefore, the interface between DSP and slow devices will be a common problem in various scientific research and development. The hardware interface method given in this article can realize the automatic state of external access to DSP, so that the high-speed DSP chip and the traditional slow input and output devices are integrated into one system, which not only effectively solves the problem of matching the access timing between DSP and various slow devices, but also has simple hardware circuit design, direct access, and easy control programming, further expanding the application space of DSP in industrial automatic control and test equipment.