The hierarchical wordline structure can improve the SRAM read and write speed and reduce the circuit dynamic power consumption

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The hierarchical wordline structure can improve the SRAM read and write speed and reduce the circuit dynamic power consumption [Copy link]

The memory using hierarchical word line structure divides the entire storage array into several identical sub-arrays. Compared with the non-hierarchical word line structure, it requires multi-level word line decoding to complete the addressing of the storage unit. As shown in Figure 1, the entire circuit adopts a multi-division array structure of hierarchical word lines.

Figure 1 Hierarchical word line structure

The use of a hierarchical word line segmentation structure can not only increase the operating speed, but also greatly reduce power consumption. This is because the word line segmentation structure makes the storage cells that were originally activated at the same time become only the storage cells in the selected block that are activated.

The specific work is: assuming that a word line is divided into n segments, if each word line originally carries Nc cells, then each segment of the word line only carries Nc/n cells after segmentation, and the word line length is also reduced to 1/n of the original. For a large-capacity memory, the word line is not simply segmented, but a hierarchical word line structure as shown in Figure 1 is used, that is, the cell array is divided into many small blocks in the word line direction, so that the local word line in each small block is shortened and the number of cells carried is reduced. A certain number of local word lines (WL) are connected to the sub-global word line (SWL) through block selection control, and several sub-global word lines are connected to the global word line (GWL) through selection control gates. The global word line is generated by decoding the high bits of the row address through the global word line decoder, which will run through the entire storage array to drive the block word line decoder of each submodule; while the block word line is generated by the global word line, block select signal and the low bits of the row address. The block word line is directly connected to the access tube of the storage unit to control whether the storage unit is enabled. Figure 2 shows the relationship between the number of word modules and power consumption through SPICE simulation.

Figure 2 Relationship between the number of submodules and power consumption

For 4Kb SRAM , the simplest two-dimensional array is divided into: 256 rows × 16 columns. Assuming that Cbl is the parasitic capacitance of each storage cell relative to the bit line, and Cwl is the parasitic capacitance of each storage cell relative to the word line, for the above two-dimensional array structure, ignoring the parasitic capacitance of the bit line and word line, the total load capacitance of each bit line is 256×Cbl, and the total load capacitance of each word line is 16×Cwl. If the entire array is divided into two 128×16b sub-arrays, and each array is equipped with row and column decoding units and precharging circuits to make them independent of each other, the bit line load is reduced to 128×Cbl, and the load on the word line in the block is also reduced to 16×Cwl, so the delay characteristics of the word line and bit line in the block will be greatly improved. Since the bit lines of the storage cells are equipped with precharging circuits, the precharging operation accounts for a considerable proportion of the power consumption of the entire chip. With a hierarchical wordline structure, only one subarray needs to be charged during read and write operations. Taking this design as an example, the capacitive load for each read and write operation is only 128×16×2×Cbl＋16×Cwl=4096×Cbl＋16×Cwl, and for an array of 256 rows×512 columns, the corresponding charge/discharge load capacitance is: 1024×64×2×Cbl＋64×Cwl=131072×Cbl＋64×Cwl. From the approximate expression of static CMOS circuit power consumption: P = C × (VDD) × f,

it can be seen that the hierarchical wordline structure not only improves the read and write speed of SRAM, but also reduces the dynamic power consumption of the circuit.

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The use of a hierarchical word line division structure can not only increase the operating speed, but also greatly reduce power consumption. This is because the word line division structure makes the storage cells that were originally activated at the same time become only the storage cells in the selected block are activated.