Xilinx introduces the industry\'s first automated fine-grained clock gating solution that reduces dynamic power consumption by up to 30% for Virtex®-6 and Spartan®-6 FPGA designs. Xilinx intelligent clock gating optimizations are automatically applied to the entire design, without adding more new tools or steps to the design flow, and without changing existing logic or clocks, thus avoiding design modifications. In addition, the solution preserves timing results in most cases.
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