MSP430F5529 clock 25MHz setting method

火辣西米秀

MSP430F5529 clock 25MHz setting method [Copy link]

The launchpad of MSP430F5529 is a development kit that TI gives away more frequently. At least everyone in our lab has one. Many people think it is slow. Indeed, compared with the speed of STM32F103 (72MHz) and STM32F407 (168MHz), the MSP430F5529 with a default main frequency of only 1MHz is just a younger brother, and the processing bit width is only 16 bits, and it does not support bit-banding operations. However, the ultra-low power consumption is enough to make it gain a foothold in the microcontroller industry. Let's stop talking nonsense and get to the point.

This time I want to share with you the frequency-upgrading solution of MSP430F5529 mentioned in the title.

To increase the frequency, we must first be able to "see" the system frequency. TI engineers have fully considered this issue and they have pins that can directly output clock signals!!!

The following description is in the Terminal Functions of the chip datesheet:

So we can output the clock signal by setting the corresponding state, and configure the IO to output + function multiplexing

Above we have realized the output of the clock. By measuring the above three IOs, we can get different clocks of the system. The next step is to configure the clock

The main thing is to configure some registers of UCS (Unified Clock System (UCS)). But before that, we have to increase the core voltage. In order to save power, the core voltage of 430 is set to 1.8V by default. The method of increasing the core voltage is mentioned in section 2.2.4 of the user manual.

The first step to enable PMM management is to unlock it. Write 0xA5 to the upper 8 bits of the PMMCTL0 register and then set the core voltage level to level 3 (the official manual mentions the relationship between frequency and core voltage).

I have to mention here that I can't achieve the desired effect by calling the official SetVcore() function. I don't know why. If anyone knows, please give me some advice.

At this point, our core voltage has been set. The next step is the clock configuration. Other experts have mentioned a lot. I just followed the method of an expert. It is not original! It is just an understanding of the ideas of predecessors.. The code is as follows

The first step is to set SCG0 in the SR register to 1. I guess the purpose here should be

I guess the purpose of this step should be to turn off the phase-locked loop. At the same time, after turning off this clock, the system clock should automatically switch to the backup clock. After turning this off, you can start setting the clock. UCSCTL0 directly turns off the output of DCO

Checking the chip's technical manual, I found that 0x60 (DCORSEL_6) is indeed the best solution! At the same time, 0x50 (DCORSEL_5) and 0x70 (DCORSEL_7) are also options!

Then understand the next step UCSCTL2 = FLLD_1 | 380;

Next, let's take a look at what these bits are set to.

With these default settings

Initially judged that the clock comes from XT1CLK

XT1 is the external crystal oscillator we enabled earlier P5.4 P5.5

Then we open the launchpad manual and find that the clock section does indeed confirm that XTL1 is a 32.768KHz crystal oscillator.

The bypass of XT1 is set to 0 by default. The complete clock signal should be like this

The effect is achieved like this

The oscilloscope used here is Loto's virtual oscilloscope OSC802

The pin of the oscilloscope is connected to the P2.2 pin. I have only recently started to pick up 430, and I am not very familiar with many things. Mistakes are inevitable. Please give me some advice!