How to improve the hardware and software architecture of embedded minimum systems?

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How to improve the hardware and software architecture of embedded minimum systems? [Copy link]

1. Introduction

　　With the rapid development of embedded-related technologies, the functions of embedded systems are becoming more and more powerful, and the application interfaces are becoming richer. Designing specific embedded minimum systems and application systems according to the needs of actual applications is the key to embedded system design. At present, in the process of embedded system development, developers often put a lot of energy into the connection between the embedded microprocessor MPU (Micro Processing Unit) and many peripherals and the development of application codes, while ignoring the research on the most basic and core parts of the embedded system.

　　Currently in the embedded field, ARM (Advanced RISC Machines) processors are widely used in various embedded devices. Since the ARM embedded architecture is similar and has common peripheral circuits, and the design principles and methods of the embedded minimum system of the ARM core are basically the same, the research on the embedded minimum system is of vital importance in the development of the entire system. This paper takes the ARM-based embedded minimum system as a platform and studies the architecture of the embedded minimum system from both hardware and software aspects. The hardware aspect mainly introduces the interface technology between the ARM processor and the typical external memory, and the software aspect focuses on a detailed analysis of the startup architecture of the embedded minimum system.

　　2. Embedded Minimum System

　　The embedded minimum system is the minimum module configuration that can make the system run while reducing the upper-level applications as much as possible. For a typical embedded minimum system, taking the ARM processor as an example, its constituent modules and their functions are shown in Figure 1, where the ARM microprocessor, FLASH and SDRAM modules are the core parts of the embedded minimum system.

　　Clock module - usually multiplied by the ARM internal phase-locked loop to provide the clock frequency input required for the operation of each module of the system

　　Flash storage module - stores boot code, operating system and user application code

　　SDRAM module - provides dynamic storage space for system operation and is the main area for system code operation

　　JTAG module——to download and debug program code

　　UART module - realize terminal display of debugging information

　　Reset module——reset the system

　　3. External memory interface technology

　　The interface technology between ARM processor and external memory (Flash and SDRAM) is the key to the hardware design of embedded minimum system. Choosing a reasonable interface method according to needs can effectively improve the overall performance of embedded system.

　　3.1 Introduction to Common External Storage

　　(1) Nor Flash and Nand Flash

　　Nor Flash is also called linear Flash. It has high reliability, fast random read speed, and the feature of on-chip execution (XIP, eXecute In Place), so that the application can run directly in the Flash memory without having to read the code into the system RAM. It is often used in situations where there are few erase and program operations and the code can be executed directly.

　　Nand Flash is an ideal solution for high data storage density. It is generally used for data storage and file storage. It is erased in blocks and has the advantage of fast erasing speed.

　　(2) Synchronous dynamic memory SDRAM

　　SDRAM (Synchronous Dynamic Random Access Memory) is an improvement on the early DRAM. It is a synchronous memory and introduces the CLK signal in the interface signal. All data, address and control signals are aligned with the rising edge of CLK. In addition, SDRAM also introduces a command controller inside. The processor accesses SDRAM by sending commands to the command controller.

　　3.2 ARM processor and Flash interface technology

　　3.2.1 ARM processor and Nor Flash interface technology

　　Nor Flash has an SRAM interface and has enough address pins to directly address the storage cells inside the memory. In the actual system, the connection method between the ARM processor and the Nor Flash can be selected as needed. Figure 2 shows two different connection methods between the ARM processor and the Nor Flash in the case of an embedded minimum system containing two Nor Flashes.

　　1) Dual Flash independent chip select

　　This method treats the two Nor Flash chips as independent units. According to different application requirements, the boot code can be stored in one Flash, and the file system can be established in the other Flash to store the application code. This method is easy to operate and manage.

　　(2) Dual Flash unified chip select

　　This method combines two Nor Flash chips into one unit for processing. The ARM processor accesses them as a parallel processing unit. In this example, two 8-bit Nor Flash chips SST39VF1601 are used as a 16-bit unit for processing. This can be used as a reference for the connection method of N (N>2) blocks of Flash.

　　3.2.2 ARM processor and Nand Flash interface technology

　　Nand Flash interface signals are relatively few, and the address, data and command buses are multiplexed. The Nand Flash interface is essentially an I/O interface. When the system accesses data from Nand Flash, it needs to send relevant commands and parameters to Nand Flash first, and then perform corresponding data operations. There are three main ways to connect ARM processors to Nand Flash:

　　Using GPIO pins to control the various signals of Nand Flash can fully utilize the performance of NAND devices when the speed requirement is relatively low. It will be very convenient to meet the time domain requirements of NAND devices, making it easy for ARM processors to control NAND devices. This method requires the processor to provide sufficient GPIO.

　　(2) Use logical operations to connect

　　In this mode, the processor's read and write enable signals drive the corresponding read and write signals of the NAND device after performing a logical operation with the chip select signal CS. Example b in Figure 3 shows the connection between the ARM7TDMI series processor S3C44B0 of SamSung and the Nand Flash K9F2808U0C.

　　(3) Direct chip enable

　　Some ARM processors, such as S3C2410, provide corresponding control registers for NAND devices. Through the control registers, the ARM processor can drive the corresponding signals of the NAND device. This method makes the connection between the ARM processor and the NAND device simple and standardized. Example c in Figure 3 shows the connection between the ARM processor S3C2410 and the Nand Flash K9F2808U0C.

　　3.3 ARM processor and SDRAM interface technology

　　The external dynamic memory module of the embedded minimum system generally uses SDRAM. Most of the current ARM processors have an integrated SDRAM controller, which can easily access every byte inside the SDRAM. In actual development, one or more SDRAMs can be selected as needed. Figure 4 shows two commonly used interface methods.

　　How to improve the hardware and software architecture of embedded minimum systems?

　　(1) Monolithic SDRAM

　 Example a shows the connection between an ARM processor S3C44B0 and a 16-bit SDRAM K4S641632d. This connection is often used in embedded systems that have strict size restrictions and low requirements on dynamic memory capacity.

　　(2) Use two 16-bit SDRAM chips together

　　When two 16-bit SDRAMs are combined into a 32-bit SDRAM, the address line A2 of the ARM processor is connected to the address line A0 of the SDRAM, and the remaining addresses are incremented in sequence. This is because the byte is the only unit of storage capacity in the SDRAM, and the SDRAM is 32 bits wide at this time.

　　The BA address line of SDRAM is the address line of its internal Bank, representing the highest bit of SDRAM memory. In Figure 4, the total size of SDRAM in example b is 64M (64M= ), which requires A25-A0 pins to address, so BA1-BA0 are connected to A25-A24 pins. It should also be noted that the row address and column address of SDRAM memory are multiplexed, so the number of address lines is generally less than 26. For specific connections, please refer to the relevant manuals of ARM processor and SDRAM.

　　It is worth noting that some ARM processors, such as the ARM940T series processor S3C2510 of SamSung, have address buses that are different from other standard ARM processors. Its address lines are divided into two types: internal address lines and external address lines. According to the width of the connected memory data bus, the internal address lines are shifted accordingly and correspond to the external address lines A23-A0, thereby providing fixed address lines A23-A0 to the outside. Its essence is consistent with that of typical ARM processors.

　　4. Embedded system startup architecture

　　Boot architecture is a key technology of embedded systems. Mastering the boot architecture is of great significance to understanding the operating principle of embedded systems. When an embedded system starts up, there are two main architectures for boot code, operating system operation, and application loading. One is the architecture that boots directly from Nor Flash, and the other is the architecture that boots directly from Nand Flash.

　　It should be noted that there are many situations in the process of embedded system booting. For example, the boot code BootRom of vxWorks can be compressed or uncompressed, resident or non-resident. The operating system itself is also stored in compressed image format. Therefore, the boot code needs to be processed accordingly according to different situations during execution and loading.

　　4.1 Boot from Nor Flash

　　Nor Flash has the feature of in-chip execution (XIP, eXecute In Place), and is often used as the first choice for storing boot code in embedded systems. The architecture booting from Nor Flash can be further divided into the boot architecture using only Nor Flash and the boot architecture using Nor Flash and Nand Flash together. Figure 5 shows the principle block diagram of these two boot architectures.

　　4.1.1 Using Nor Flash alone

　　In this architecture, the boot code, operating system, and application code coexist in the same Nor Flash. After the system is powered on, the boot code is first executed in the Nor Flash, and then the operating system and application code are loaded into the higher-speed SDRAM for execution. Another feasible architecture is to execute the boot code and operating system in the Nor Flash, and only load the application code into the SDRAM for execution.

　　This architecture makes full use of the characteristics of Nor Flash in-chip execution, which can effectively improve system performance. However, the disadvantage is that as the capacity of the operating system and application code increases, more expensive Nor Flash is needed to support it.

　　4.1.2 Using Nor Flash and Nand Flash Together

　　The use of Nor Flash alone will increase the cost of the product for applications with large amounts of code. One way to improve this is to use an architecture that uses Nor Flash and Nand Flash together. In this architecture, a Nand Flash is added. The Nor Flash (2M or 4M) stores the boot code and the operating system (the operating system can be stored in the Nor Flash or Nand Flash depending on the amount of code), while the Nand Flash stores the application code. The Nand Flash capacity can be changed accordingly based on the amount of application code stored.

　　After the system is powered on, the boot code is directly executed in the Nor Flash, and the operating system and application code in the Nand Flash are loaded into the higher-speed SDRAM for execution. It is also possible to execute the boot code and operating system in the Nor Flash, and only load the application code in the Nand Flash into the SDRAM for execution. This architecture is one of the most widely used boot architectures in current embedded systems.

　　4.1.2 Booting from Nand Flash

　　Some processors, such as the ARM920T series processor S3C2410 of Samsung Sung, support the mode of booting from Nand Flash. Its working principle is to load the first 4KB code stored in Nand Flash into an address called Steppingstone (BootSRAM), and then start to execute the boot code to complete the loading of the operating system and application. This method requires a NAND controller inside the processor and a certain amount of additional SRAM space. It has certain limitations and is rarely used in actual development.

　　5. Conclusion

　　The author's innovation: Based on the interoperability of ARM architecture, the author takes the ARM-based embedded minimum system as the platform and studies its architecture from both hardware and software aspects. In terms of hardware, the author explains the interface between ARM processor and common external memory, and in terms of software, the author gives the typical startup architecture of the embedded minimum system and its selection criteria.