Detailed analysis of the improvement of the software and hardware architecture of the ARM embedded minimum system

Jacktang

Detailed analysis of the improvement of the software and hardware architecture of the ARM embedded minimum system [Copy link]

With the rapid development of embedded-related technologies, the functions of embedded systems are becoming more and more powerful, and the application interfaces are becoming more and more abundant. Designing specific embedded minimum systems and application systems according to the needs of actual applications is the key to embedded system design. At present, in the process of embedded system development, developers often put a lot of energy into the connection between embedded microprocessorMPU (Micro Processing Unit) and many peripherals and the development of application code, but ignore the research on the most basic and core parts of embedded systems.

Currently in the embedded field, ARM (Advanced RISC Machines) processors are widely used in various embedded devices. Since the ARM embedded system architecture is similar and has common peripheral circuits, and the design principles and methods of the embedded minimum system of the ARM core are basically the same, the research on the embedded minimum system is of vital importance in the development of the entire system. This paper takes the ARM-based embedded minimum system as a platform and studies the architecture of the embedded minimum system from both hardware and software aspects. The hardware aspect mainly introduces the interface technology between the ARM processor and the typical external memory, and the software aspect focuses on the detailed analysis of the startup architecture of the embedded minimum system.

2. Embedded Minimum System

The embedded minimum system is the minimum module configuration that can enable the system to run while reducing the upper-level applications as much as possible. For a typical embedded minimum system, taking the ARM processor as an example, its constituent modules and their functions are shown in Figure 1, where the ARM microprocessor, FLASH and SDRAM modules are the core parts of the embedded minimum system. :

Clock module - usually multiplied by the ARM internal phase-locked loop to provide the clock frequency input required for the operation of each module of the system

Flash storage module - stores startup code, operating system and user application code

[p=30, null, , 34, 34)] SDRAM module - provides dynamic storage space for system operation and is the main area for system code operation

JTAG module - realizes the download and debugging of program code

UART module - realizes the terminal display of debugging information

Reset module - realizes the reset of the system

[p=30, null, 3. External Memory Interface Technology The interface technology between ARM processor and external memory (Flash and SDRAM) is the key to the hardware design of embedded minimum system. Choosing a reasonable interface method according to the needs can effectively improve the overall performance of the embedded system.

3.1 Introduction to Common External Memory

(1) Nor Flash and Nand Flash

Nor Flash, also known as Linear Flash, has high reliability, fast random read speed, and features on-chip execution (XIP, eXecute In Place) feature, so that the application can run directly in the Flash memory, without having to read the code into the system RAM. It is often used in situations where there are fewer erase and programming operations and the code is executed directly.

Nand Flash is an ideal solution for high data storage density. It is generally used for data storage and file storage. It is erased in blocks and has the advantage of fast erase speed.

(2) Synchronous dynamic memory SDRAM

SDRAM (Synchronous Dynamic Random Access Memory) is an improvement on the early DRAM. It is synchronous memory and introduces the CLK signal in the interface signal. All data, address and control signals are aligned with the rising edge of CLK. In addition, SDRAM also introduces a command controller internally. The processor accesses SDRAM by sending commands to the command controller.

3.2 ARM processor and Flash interface technology

3.2.1 ARM processor and Nor Flash interface technology

[p=30, null, Nor Flash has an SRAM interface and has enough address pins to directly address the storage units inside the memory. In the actual system, the connection method between the ARM processor and the Nor Flash can be selected as needed. Figure 2 shows two different connection methods between the ARM processor and the Nor Flash in the case of an embedded minimum system containing two Nor Flashes.

1) Dual Flash independent chip select

This method treats the two Nor Flash chips as an independent unit. According to different application needs, the boot code can be stored in one Flash, and the file system can be established in another Flash to store the application code. This method is convenient to operate and easy to manage.

(2) Dual Flash unified chip select

This method combines two Nor Flash chips into one unit for processing. The ARM processor accesses them as a parallel processing unit. In this example, two 8-bit Nor Flash chips SST39VF1601 are used as a 16-bit unit for processing. This can be used as a reference for the connection method of N (N>2) blocks of Flash.

3.2.2 ARM processor and Nand Flash interface technology

Nand Flash interface signals are relatively few, and the address, data and command bus is multiplexed. The Nand Flash interface is essentially an I/O interface. When the system accesses data to Nand Flash, it needs to first send relevant commands and parameters to the Nand Flash, and then perform corresponding data operations. There are three main ways to connect the ARM processor to Nand Flash, as shown in Figure 3:

Using the GPIO pin method to control the various signals of Nand Flash can fully exert the performance of NAND devices when the speed requirements are relatively low. It will be very convenient in meeting the time domain requirements of NAND devices, making it easy for ARM processors to control NAND devices. This method requires the processor to provide sufficient GPIO.

(2) Connect using logical operation

In this method, the processor's read and write enable signals drive the corresponding read and write signals of the NAND device after logical operation with the chip select signal CS. Example b in Figure 3 shows the connection between the ARM7TDMI series processor S3C44B0 of SamSung and the Nand Flash K9F2808U0C.

(3) Direct chip enable

Some ARM processors, such as S3C2410, provide corresponding control registers for NAND devices. Through the control registers, the ARM processor can drive the corresponding signals of the NAND device. This method makes the connection between the ARM processor and the NAND device simple and standardized. Example c in Figure 3 shows the connection between the ARM processor S3C2410 and the Nand Flash K9F2808U0C.

3.3 ARM processor and SDRAM interface technology

The external dynamic memory module of the embedded minimum system generally uses SDRAM. Most of the current ARM processors have an integrated SDRAM controller, which can easily access every byte inside the SDRAM. In actual development, one or more SDRAMs can be selected as needed. Figure 4 shows two commonly used interface methods.