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Problems with using modelsim [Copy link]

I found that when using modelsim simulation, if there is an always block without a sensitive signal list in the project to be tested and the testbench, or there is an always block without a delay in the testbench, the simulation will get stuck after runall. It takes a long time to break after clicking break. After breaking, the simulation basically stops at the problematic always block. Is this normal?
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If you post the code, it seems that there is feedback in your combinational logic, which causes modelsim to lock up.  Details Published on 2019-4-14 10:53
 

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If you post the code, it seems that there is feedback in your combinational logic, which causes modelsim to lock up.
This post is from FPGA/CPLD
 
 

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