FPGA configuration peripheral circuit design conflicts and solutions

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FPGA configuration peripheral circuit design conflicts and solutions [Copy link]

The entire process of FPGA power-on configuration takes about 200ms~2s. During this time, most of the other peripheral circuit devices have been powered on and are working normally, while the general I/O pins of the FPGA are still in a weak pull-up (HSWAPEN=0) or in an indeterminate state (HSWAPEN=1). When designing, it is necessary to consider whether there is a timing conflict between the power-on initialization of these devices and the general I/O pins of the FPGA. For example: when powered on, the peripheral devices require that the I/O pins are all low-level, while the FPGA defaults to weak pull-up, resulting in a conflict in the initialization level; the peripheral devices require that the configuration pins be collected immediately after power-on reset for initialization, while the FPGA is still in the configuration state and cannot correctly pull up or pull down the I/O pins, resulting in device initialization errors; the peripheral devices require that the clock phase lock be required before power-on initialization, and the FPGA cannot generate the clock during configuration, resulting in device initialization failure, etc. There are roughly three ways to resolve these conflicts, but the premise is to correctly configure the HSWAPEN pin. Because after the FPGA executes the "device power-on" step (5~30ms), the state of the I/O pins it outputs can be set through HSWAPEN. Method 1: Add a pull-down resistor to the I/O pin of the FPGA, with a resistance between 1~10kΩ, determined according to actual needs. Within 10ms after power-on, the FPGA can pull the I/O pin to the level required by the user through the pull-up and pull-down resistors. This can solve the problem of peripheral circuits that power on slowly but require a fixed level, such as power amplifier transmitter switches and protection switches. Method 2: After the configuration is completed, the FPGA can generate a global reset signal to reset the peripheral circuit hardware and perform an initialization operation again. This can solve the problem that the power-on initialization of PowrerPC and ARM is very fast (it can be completed within 100ms), but the FPGA has not been configured, resulting in PowrerPC initialization errors. Moreover, this method does not require external extra pull-up and pull-down resistors, reducing the complexity of circuit design. Method 3: FPGA can generate a Power Good signal after configuration. The system will power on other peripheral devices with timing requirements based on this signal. This can solve the problem of DSP or high-speed AD devices that need to be initialized after clock locking. These three methods can also be used in combination according to specific circumstances to achieve better results.