To solve the problem of impedance continuity in PCB design, just read this article!
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Everyone knows that impedance should be continuous. However, as Luo Yonghao said, "There are always times when you step on shit in life", and there are always times when impedance cannot be continuous in PCB design. What should we do? Characteristic impedance: also known as "characteristic impedance", it is not a DC resistance, but a concept in long-distance transmission. In the high-frequency range, during signal transmission, when the signal reaches the place along the line, an instantaneous current will be generated due to the establishment of an electric field between the signal line and the reference plane (power supply or ground plane). If the transmission line is isotropic, then as long as the signal is transmitting, there will always be a current I. If the output voltage of the signal is V, during the signal transmission process, the transmission line will be equivalent to a resistor with a magnitude of V/I. This equivalent resistor is called the characteristic impedance Z of the transmission line. During the transmission process of a signal, if the characteristic impedance on the transmission path changes, the signal will be reflected at the node where the impedance is discontinuous. The factors that affect the characteristic impedance are: dielectric constant, dielectric thickness, line width, and copper foil thickness. 【1】Gradient Line Some RF device packages are small. The SMD pad width may be as small as 12 mils, while the RF signal line width may be more than 50 mils. Use gradient lines and prohibit sudden changes in line width. The gradient line is shown in the figure. The line in the transition part should not be too long. [ font=-apple-system-font, BlinkMacSystemFont, "][2]corner If the RF signal line runs at a right angle, the effective line width at the corner will increase, the impedance will be discontinuous, and signal reflection will occur. In order to reduce the discontinuity, the corners need to be processed. There are two methods: corner cutting and corner rounding. The radius of the arc angle should be large enough. Generally speaking, it is necessary to ensure that: R>3W. As shown on the right. 【3】Large pads When there is a large pad on a 50 ohm microstrip line, the large pad is equivalent to distributed capacitance, which destroys the continuity of the characteristic impedance of the microstrip line. Two methods can be used to improve it at the same time: first, thicken the microstrip line medium, and second, hollow out the ground plane under the pad, both of which can reduce the distributed capacitance of the pad. As shown in the figure below. [ font=-apple-system-font, BlinkMacSystemFont, "][4]via A via is a metal cylinder plated outside of a through hole between the top and bottom layers of a board. Signal vias connect transmission lines on different layers. Via stubs are unused portions of a via. Via pads are donut-shaped pads that connect vias to top or internal transmission lines. Isolation pads are annular gaps within each power or ground plane to prevent shorts to the power and ground planes. Parasite parameters of vias After rigorous physical theory derivation and approximate analysis, the equivalent circuit model of the via can be an inductor with a grounding capacitor connected in series at both ends, as shown in Figure 1. Equivalent circuit model of via From the equivalent circuit model, we know that the via itself has parasitic capacitance to the ground. Assuming that the diameter of the via anti-pad is D2, the diameter of the via pad is D1, the thickness of the PCB is T, and the dielectric constant of the board substrate is ε, the parasitic capacitance of the via is approximately: The parasitic capacitance of the via can cause the signal rise time to be prolonged and the transmission speed to be slowed down, thereby deteriorating the signal quality. Similarly, the via also has parasitic inductance. In high-speed digital PCBs, the harm caused by parasitic inductance is often greater than that of parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor, thereby weakening the filtering effect of the entire power system. Assume that L is the inductance of the via, h is the length of the via, and d is the diameter of the center drill hole. The approximate parasitic inductance of the via is approximately: Via is one of the important factors causing impedance discontinuity in the RF channel. If the signal frequency is greater than 1GHz, the influence of the via must be considered. Common methods to reduce via impedance discontinuity include: using padless process, selecting routing method, optimizing anti-pad diameter, etc. Optimizing anti-pad diameter is one of the most commonly used methods to reduce impedance discontinuity. Since via characteristics are related to structural dimensions such as aperture, pad, anti-pad, stacking structure, routing method, etc., it is recommended to use HFSS and Optimetrics for optimization simulation according to specific circumstances each time you design. When using a parametric model, the modeling process is very simple. During the review, PCB designers are required to provide corresponding simulation documents. The diameter of the via, the diameter of the pad, the depth, and the anti-pad will all bring changes, resulting in the severity of impedance discontinuity, reflection and insertion loss. 【5】Through-hole coaxial connector Similar to the via structure, the through-hole coaxial connector also has impedance discontinuity, so the solution is the same as the via. The common methods to reduce the impedance discontinuity of the through-hole coaxial connector are also: using a diskless process, a suitable wiring method, and optimizing the anti-pad diameter. Source: Reprinted from the Internet, if copyright is involved, please contact us to delete. BlinkMacSystemFont, "]
Parasite parameters of vias After rigorous physical theory derivation and approximate analysis, the equivalent circuit model of the via can be taken as an inductor with a grounding capacitor connected in series at both ends, as shown in Figure 1. Equivalent circuit model of vias From the equivalent circuit model, we can see that the via itself has parasitic capacitance to the ground. Assuming that the diameter of the via anti-pad is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate is ε, the parasitic capacitance of the via is approximately: The parasitic capacitance of vias can cause the signal rise time to be prolonged and the transmission speed to be slowed down, thus deteriorating the signal quality. Similarly, vias also have parasitic inductance. In high-speed digital PCBs, the harm caused by parasitic inductance is often greater than that of parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor, thereby weakening the filtering effect of the entire power system. Assume that L is the inductance of the via, h is the length of the via, and d is the diameter of the center drill hole. The approximate parasitic inductance of the via is approximately: Via is one of the important factors causing impedance discontinuity in the RF channel. If the signal frequency is greater than 1GHz, the influence of the via must be considered. Common methods to reduce via impedance discontinuity include: using padless process, selecting routing method, optimizing anti-pad diameter, etc. Optimizing anti-pad diameter is one of the most commonly used methods to reduce impedance discontinuity. Since via characteristics are related to structural dimensions such as aperture, pad, anti-pad, stacking structure, routing method, etc., it is recommended to use HFSS and Optimetrics for optimization simulation according to specific circumstances each time you design. When using a parametric model, the modeling process is very simple. During the review, PCB designers are required to provide corresponding simulation documents. The diameter of the via, the diameter of the pad, the depth, and the anti-pad will all bring changes, resulting in the severity of impedance discontinuity, reflection and insertion loss. 【5】Through-hole coaxial connector Similar to the via structure, the through-hole coaxial connector also has impedance discontinuity, so the solution is the same as the via. The common methods to reduce the impedance discontinuity of the through-hole coaxial connector are also: using a diskless process, a suitable wiring method, and optimizing the anti-pad diameter. Source: Reprinted from the Internet, if copyright is involved, please contact us to delete. BlinkMacSystemFont, "]
Parasite parameters of vias After rigorous physical theory derivation and approximate analysis, the equivalent circuit model of the via can be taken as an inductor with a grounding capacitor connected in series at both ends, as shown in Figure 1. Equivalent circuit model of vias From the equivalent circuit model, we can see that the via itself has parasitic capacitance to the ground. Assuming that the diameter of the via anti-pad is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate is ε, the parasitic capacitance of the via is approximately: The parasitic capacitance of vias can cause the signal rise time to be prolonged and the transmission speed to be slowed down, thus deteriorating the signal quality. Similarly, vias also have parasitic inductance. In high-speed digital PCBs, the harm caused by parasitic inductance is often greater than that of parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor, thereby weakening the filtering effect of the entire power system. Assume that L is the inductance of the via, h is the length of the via, and d is the diameter of the center drill hole. The approximate parasitic inductance of the via is approximately: Via is one of the important factors causing impedance discontinuity in the RF channel. If the signal frequency is greater than 1GHz, the influence of the via must be considered. Common methods to reduce via impedance discontinuity include: using padless process, selecting routing method, optimizing anti-pad diameter, etc. Optimizing anti-pad diameter is one of the most commonly used methods to reduce impedance discontinuity. Since via characteristics are related to structural dimensions such as aperture, pad, anti-pad, stacking structure, routing method, etc., it is recommended to use HFSS and Optimetrics for optimization simulation according to specific circumstances each time you design. When using a parametric model, the modeling process is very simple. During the review, PCB designers are required to provide corresponding simulation documents. The diameter of the via, the diameter of the pad, the depth, and the anti-pad will all bring changes, resulting in the severity of impedance discontinuity, reflection and insertion loss. 【5】Through-hole coaxial connector Similar to the via structure, the through-hole coaxial connector also has impedance discontinuity, so the solution is the same as the via. The common methods to reduce the impedance discontinuity of the through-hole coaxial connector are also: using a diskless process, a suitable wiring method, and optimizing the anti-pad diameter. Source: Reprinted from the Internet, if copyright is involved, please contact us to delete. "]After rigorous physical theory deduction and approximate analysis, the equivalent circuit model of the via can be an inductor with a grounding capacitor connected in series at both ends, as shown in Figure 1. Equivalent Circuit Model of Via From the equivalent circuit model, we know that the via itself has parasitic capacitance to the ground. Assuming that the diameter of the via anti-pad is D2, the diameter of the via pad is D1, the thickness of the PCB is T, and the dielectric constant of the board substrate is ε, the parasitic capacitance of the via is approximately: The parasitic capacitance of the via can cause the signal rise time to be prolonged and the transmission speed to be slowed down, thereby deteriorating the signal quality. Similarly, the via also has parasitic inductance. In high-speed digital PCBs, the harm caused by parasitic inductance is often greater than that of parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor, thereby weakening the filtering effectiveness of the entire power system. Assume that L is the inductance of the via, h is the length of the via, and d is the diameter of the center drill hole. The approximate parasitic inductance of the via is approximately: Via is one of the important factors causing impedance discontinuity in the RF channel. If the signal frequency is greater than 1GHz, the influence of the via must be considered. Common methods to reduce via impedance discontinuity include: using padless process, selecting lead-out method, optimizing anti-pad diameter, etc. Optimizing the anti-pad diameter is one of the most commonly used methods to reduce impedance discontinuity. Since the characteristics of vias are related to the structural dimensions of the aperture, pad, anti-pad, stacking structure, and wiring method, it is recommended to use HFSS and Optimetrics for optimization simulation according to the specific situation each time you design. When a parametric model is used, the modeling process is very simple. During the review, the PCB designer is required to provide the corresponding simulation documents. The diameter of the via, the pad diameter, the depth, and the anti-pad will all bring changes, resulting in impedance discontinuity, reflection, and the severity of insertion loss. 【5】Through-hole coaxial connector Similar to the via structure, the through-hole coaxial connector also has impedance discontinuity, so the solution is the same as that of the via. The common methods to reduce the impedance discontinuity of the through-hole coaxial connector are also: using a padless process, a suitable wiring method, and optimizing the anti-pad diameter. Source: Reprinted from the Internet. If copyright is involved, please contact us to delete. "]After rigorous physical theory deduction and approximate analysis, the equivalent circuit model of the via can be an inductor with a grounding capacitor connected in series at both ends, as shown in Figure 1. Equivalent Circuit Model of Via From the equivalent circuit model, we know that the via itself has parasitic capacitance to the ground. Assuming that the diameter of the via anti-pad is D2, the diameter of the via pad is D1, the thickness of the PCB is T, and the dielectric constant of the board substrate is ε, the parasitic capacitance of the via is approximately: The parasitic capacitance of the via can cause the signal rise time to be prolonged and the transmission speed to be slowed down, thereby deteriorating the signal quality. Similarly, the via also has parasitic inductance. In high-speed digital PCBs, the harm caused by parasitic inductance is often greater than that of parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor, thereby weakening the filtering effectiveness of the entire power system. Assume that L is the inductance of the via, h is the length of the via, and d is the diameter of the center drill hole. The approximate parasitic inductance of the via is approximately: Via is one of the important factors causing impedance discontinuity in the RF channel. If the signal frequency is greater than 1GHz, the influence of the via must be considered. Common methods to reduce via impedance discontinuity include: using padless process, selecting lead-out method, optimizing anti-pad diameter, etc. Optimizing the anti-pad diameter is one of the most commonly used methods to reduce impedance discontinuity. Since the characteristics of vias are related to the structural dimensions of the aperture, pad, anti-pad, stacking structure, and wiring method, it is recommended to use HFSS and Optimetrics for optimization simulation according to the specific situation each time you design. When a parametric model is used, the modeling process is very simple. During the review, the PCB designer is required to provide the corresponding simulation documents. The diameter of the via, the pad diameter, the depth, and the anti-pad will all bring changes, resulting in impedance discontinuity, reflection, and the severity of insertion loss. 【5】Through-hole coaxial connector Similar to the via structure, the through-hole coaxial connector also has impedance discontinuity, so the solution is the same as that of the via. The common methods to reduce the impedance discontinuity of the through-hole coaxial connector are also: using a padless process, a suitable wiring method, and optimizing the anti-pad diameter. Source: Reprinted from the Internet. If copyright is involved, please contact us to delete. "]The parasitic capacitance of vias can cause the signal rise time to be prolonged and the transmission speed to be slowed down, thus deteriorating the signal quality. Similarly, vias also have parasitic inductance. In high-speed digital PCBs, the harm caused by parasitic inductance is often greater than that of parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor, thereby weakening the filtering effect of the entire power supply system. Assume that L is the inductance of the via, h is the length of the via, and d is the diameter of the center drill hole. The approximate parasitic inductance of the via is approximately: Via is one of the important factors causing impedance discontinuity in the RF channel. If the signal frequency is greater than 1GHz, the influence of the via must be considered. The common methods to reduce the impedance discontinuity of vias include: using padless process, selecting the lead-out method, optimizing the anti-pad diameter, etc. Optimizing the anti-pad diameter is one of the most commonly used methods to reduce impedance discontinuity. Since the characteristics of vias are related to the structural dimensions such as aperture, pad, anti-pad, stacking structure, and wiring method, it is recommended to use HFSS and Optimetrics for optimization simulation according to the specific situation each time you design. When using a parametric model, the modeling process is very simple. During the review, PCB designers are required to provide corresponding simulation documents. The diameter of the via, pad diameter, depth, and anti-pad will all bring changes, resulting in impedance discontinuity, reflection, and insertion loss severity. 【5】Through-hole coaxial connector Similar to the via structure, the through-hole coaxial connector also has impedance discontinuity, so the solution is the same as that of the via. The common methods to reduce the impedance discontinuity of the through-hole coaxial connector are also: using a padless process, a suitable wiring method, and optimizing the anti-pad diameter. Source: Reprinted from the Internet. If copyright is involved, please contact us to delete. "]The parasitic capacitance of vias can cause the signal rise time to be prolonged and the transmission speed to be slowed down, thus deteriorating the signal quality. Similarly, vias also have parasitic inductance. In high-speed digital PCBs, the harm caused by parasitic inductance is often greater than that of parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor, thereby weakening the filtering effect of the entire power supply system. Assume that L is the inductance of the via, h is the length of the via, and d is the diameter of the center drill hole. The approximate parasitic inductance of the via is approximately: Via is one of the important factors causing impedance discontinuity in the RF channel. If the signal frequency is greater than 1GHz, the influence of the via must be considered. The common methods to reduce the impedance discontinuity of vias include: using padless process, selecting the lead-out method, optimizing the anti-pad diameter, etc. Optimizing the anti-pad diameter is one of the most commonly used methods to reduce impedance discontinuity. Since the characteristics of vias are related to the structural dimensions such as aperture, pad, anti-pad, stacking structure, and wiring method, it is recommended to use HFSS and Optimetrics for optimization simulation according to the specific situation each time you design. When using a parametric model, the modeling process is very simple. During the review, PCB designers are required to provide corresponding simulation documents. The diameter of the via, pad diameter, depth, and anti-pad will all bring changes, resulting in impedance discontinuity, reflection, and insertion loss severity. 【5】Through-hole coaxial connector Similar to the via structure, the through-hole coaxial connector also has impedance discontinuity, so the solution is the same as that of the via. The common methods to reduce the impedance discontinuity of the through-hole coaxial connector are also: using a padless process, a suitable wiring method, and optimizing the anti-pad diameter. Source: Reprinted from the Internet. If copyright is involved, please contact us to delete. "]Similar to the via structure, the through-hole coaxial connector also has impedance discontinuity, so the solution is the same as the via. The common methods to reduce the impedance discontinuity of the through-hole coaxial connector are also: using a diskless process, a suitable wiring method, and optimizing the anti-pad diameter. Source: Reprinted from the Internet, if copyright is involved, please contact us to delete. "]Similar to the via structure, the through-hole coaxial connector also has impedance discontinuity, so the solution is the same as the via. The common methods to reduce the impedance discontinuity of the through-hole coaxial connector are also: using a diskless process, a suitable wiring method, and optimizing the anti-pad diameter. Source: Reprinted from the Internet, if copyright is involved, please contact us to delete.
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