Impedance control of through holes in PCB design and its impact on signal integrity

Vias act as conductors in connecting traces on different layers of a multi-layer PCB(A printed circuit board). At low frequencies, vias do not affect signal transmission. However, as frequency increases (above 1 GHz) and the rising edge of the signal becomes steeper (up to 1ns), vias cannot simply be viewed as a function of the electrical connection, but rather the impact of vias on signal integrity must be carefully considered Impact. Vias appear as impedance discontinuities in transmission lines, causing signal reflections. However, the problems caused by vias are more focused on parasitic capacitance and parasitic inductance. The main impact of via parasitic capacitance on the circuit is to prolong the rise time of the signal and reduce the operating speed of the circuit. However, parasitic inductance will weaken the bypass circuit and reduce the filtering function of the entire power system.

Impact of Vias on Impedance Continuity

According to the TDR (time domain reflectometry) curves when the via is present and when the via is not present, significant signal delay does occur in the absence of the via. In the absence of a via, the time span of signal transmission to the second test hole is 458ps, while in the presence of a via, the time span of signal transmission to the second test hole is 480ps. Therefore, the signal is delayed by 22ps through the leads.

Signal delay is mainly caused by the parasitic capacitance of the via, which can be obtained by the following formula:

In this formula, d 2 refers to the pad diameter (mm) on the ground, d  1 refers to the diameter of the pad through hole (mm), T is the PCB board thickness (mm), ε r  is the dielectric constant of the reference layer C to parasitic capacitance (pF).

In this discussion, the length of the via is 0.96mm, the diameter of the via is 0.3mm, the diameter of the pad is 0.5mm, and the dielectric constant is 4.2. Involving the above formula, the calculated parasitic capacitance is about 0.562pF. For a signal transmission line with a resistance of 50Ω, this via will cause the rise time of the signal to change, and the change is calculated by the following formula:

According to the formula introduced above, the rise time change caused by the via capacitance is 30.9ps, which is 9ps longer than the test result (22ps), which shows that there is indeed a change between the theoretical results and the actual results.

In short, the signal delay caused by via parasitic capacitance is not very obvious. However, when it comes to high-speed circuit design, special attention should be paid to multi-layer transitions that apply vias in traces.

Vias have parasitic inductance that can cause more circuit damage than parasitic capacitance. The parasitic inductance of the via can be found by the following formula:

In this formula, L represents the parasitic inductance of the through hole (nH), h represents the length of the through hole (mm), and d represents the diameter of the through hole (mm). The equivalent impedance caused by via parasitic inductance can be calculated by the following formula:

The rise time of the test signal is 500ps, and the equivalent impedance is 4.28Ω. However, the impedance change caused by the through hole reaches more than 12Ω, which shows that there is a huge difference between the measured value and the theoretical calculated value.

Effect of Via Diameter on Impedance Continuity

Based on a series of experiments, it can be concluded that the larger the diameter of the via, the greater the discontinuity of the via. In the high-frequency, high-speed PCB design process, impedance changes are usually controlled within the range of ±10%, otherwise signal distortion may occur.

Effect of Pad Size on Impedance Continuity

Parasitic capacitance has a great influence on the resonance point in the high-frequency signal band, and the bandwidth will shift with the parasitic capacitance. The primary factor affecting parasitic capacitance is pad size, which has the same impact on signal integrity. Therefore, the larger the pad diameter, the stronger the impedance discontinuity will be.

When the pad diameter changes in the range of 0.5mm to 1.3mm, the impedance discontinuity caused by the via hole will continue to decrease. When the pad size increases from 0.5mm to 0.7mm, the impedance will have a relatively large change amplitude. As the pad size continues to increase, the change in via impedance will become smoother. Therefore, the larger the pad diameter, the smaller the impedance discontinuity caused by the via.

Return path through signal

The basic principle of return signal flow is that high-speed return signal current flows along the path of lowest inductance. Because the PCB board contains more than one ground plane, the return signal current flows directly along a path under the signal line and the ground plane closest to the signal line. When all signal current flows along the same plane as it flows from one point to another, if the signal flows from one point to another through a via, then the return signal current will not jump when grounded.

In high-speed PCB designs, a return path can be provided through the signal current to eliminate impedance mismatch. Around the via, the ground via can be designed to provide a return path for signal current and create an inductive loop between the signal via and the ground via. Even if the impedance is discontinuous due to the effect of vias, current will be able to flow to the inductive loop, thus improving signal quality.

Via Signal Integrity

S-parameters can be used to evaluate the impact of vias on signal integrity and represent the characteristics of all components in the channel, including loss, attenuation, and reflection. According to a series of experiments utilized in this article, it is shown that grounded vias can reduce transmission losses, and if more grounded vias are formed around the vias, the transmission loss will be lower. The losses caused by vias can be reduced to some extent by adding ground holes around them.

Two conclusions can be drawn from the above:
1. The impedance discontinuity caused by the through hole is affected by the diameter of the through hole and the size of the pad. The larger the via diameter and pad diameter, the more serious the impedance discontinuity caused will be. The impedance discontinuity caused by vias generally decreases as pad size increases.
2. Adding ground vias can significantly improve the via impedance discontinuity, which can be controlled within the range of ±10%. Additionally, adding ground vias can significantly improve signal integrity.

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