Application of MSP430F5xxx in the highway toll collection system (ETC)
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The method of using MSP430F5xxx to implement real-time HDLC encoding and decoding in ETC system. MSP430F5xxx is the latest product series of TI's MSP430 family. It adopts advanced 0.18 process and consumes an astonishing 160uA current per MIPS. At the same time, F5xx products are equipped with efficient and flexible DMA modules, which only takes 2 clock cycles to move 16bit data. This article gives a method of combining F5xx's DMA, TimerA, CRC16 and SPI to achieve almost real-time HDLC FM0 soft decoding and a convenient FM0 encoding method using SPI. This article includes two related example codes. Introduction to MSP430 TI's MSP430 microcontroller product series has a 16-bit RSIC architecture and ultra-low power consumption. As the latest product series of MSP430, F5xxx uses 0.18um process for the first time, and the current consumed by 1MIPs is as low as an astonishing 160uA, and the main frequency reaches 25MIPs. At the same time, MSP430F5xxx provides a wealth of on-chip functional modules, such as hardware RTC, 12-bit ADC, flexible clock system, hardware CRC16, power management module and multi-channel flexible and powerful DMA, supporting data exchange in standby mode. Introduction to the Expressway Toll Collection System (ETC) The Expressway Toll Collection System (also known as the Electronic Toll Collection System, or ETC System for short) is an intelligent transportation subsystem that uses RFID technology to realize automatic toll collection without stopping. The system automatically completes the toll collection process through dedicated short-range communication between the Road Side Unit (RSU) and the on-board electronic tag OBU (On Board Unit) without the need for the driver to stop and the toll collector to operate. ETC vehicle-mounted unit structure Figure 1. ETC OBU structure diagram As shown in Figure 1, OBU consists of a battery system, MCU, RF, display and card reader (ESAM card, CPU card, RF card). As the center of the entire system, MCU is responsible for managing display, card reader and data processing and exchange with the RF part. FM0 encoding method introduction When the vehicle passes through the toll station, OBU and RSU use 5.8G carrier modulation to exchange data at high speed. The data adopts HDLC FM0 modulation. FM0 encoding follows the following three rules: A. A level jump in a cycle represents "0"; B. No level jump in a cycle represents "1"; C. The levels of two adjacent cycles are opposite. Please refer to Figure 2 for the data format Figure 2. FM0 encoding method Challenges of on-board electronic tags (OBU) to MCU The on-board electronic tag system poses two challenges to the MCU. One is low power consumption; the other is high-speed data communication capability. The battery of the on-board electronic tag is required to have a life of more than 5 years or be able to support more than 10,000 transactions. The low power design of the entire system has become the primary task of engineers. Secondly, the baud rate of RSU to OBU downlink data reaches 256Kbps, and the baud rate of uplink data is 512Kbps. Since the vehicle travel time is very short, OBU needs to respond quickly to RSU data and commands. The maximum length of a data packet can reach 1Kbits, and the OBU is not allowed to decode after receiving the entire data packet. This requires the MCU to have the ability to encode and decode in real time. In general, the soft decoding of FM0 needs to obtain the level width of the data to achieve decoding. There are usually two ways. One is that the Timer captures the data edge, and then the software determines the width between the data edges in the interrupt. The other is to sample the level of the data port line at a fixed time and obtain the level width by counting. The ETC downlink data rate reaches 256Kbps. For data "0", the width between the data jump edges is only 2uS. For data "1", the data edge width is only 4uS. Taking the first method as an example, the traditional soft decoding process is as follows: Figure 3. Timer capture interrupt mode As shown in Figure 2, during the data reception process, the Timer will capture a data edge every 2uS or 4uS and save the data edge to the corresponding register. Therefore, the data in the Timer capture register will be updated at the fastest every 2uS. This requires the CPU speed to be fast enough to complete the decoding process within at least 2uS. Otherwise, the data in the Timer capture register will be overwritten by the new data, causing decoding errors. Assuming that the MCU needs 50 cycles to complete 1 bit decoding, then the MCU main frequency must reach at least 25MIPS to achieve real-time decoding. Usually, we will select MCUs with a main frequency of more than 40MIPs, and the power consumption of these high-speed MCUs is often difficult to meet the requirements of the ETC system. Therefore, many ETC manufacturers use dual MCUs, with a high-speed MCU to implement FM0 real-time encoding and decoding, and another low-power MCU, usually MSP430, to manage the power consumption of the entire system. This increases the cost and complexity of the system. The advent of MSP430F5xxx can simultaneously meet all the challenges of the ETC system to MCU and solve the customer's troubles. Method of using F5xxx on-chip DMA and TimerA capture function to implement FM0 real-time decoding MSP430F5xxx's excellent low power consumption characteristics can meet the low power consumption requirements of ETC OBU. As the latest product series of MSP430, F5xxx adopts 0.18um process for the first time. The current consumed by 1MIPs is as low as 160uA. The on-chip PMM (power management module) allows users to flexibly adjust the core voltage according to the MCU load to ensure the lowest power consumption. In addition, it has multiple low-power states. In the typical LPM3 mode, the power consumption is only 2uA when the RTC is turned on and the RAM data is retained. In addition to the excellent low-power characteristics, although the main frequency of MSP430F5xx can only reach 25MIPS at most, it has a flexible multi-channel DMA and can be linked with the Timer to realize automatic data movement without interfering with the CPU. This greatly enhances the data throughput capacity of the MCU, making the main frequency no longer a bottleneck, and completing the near-real-time decoding of FM0. In addition, the hardware CRC16 module allows the MCU to complete data verification by simply operating the register. The real-time decoding process using DMA and CRC16 is shown in Figure 4: Figure 4. Decoding method of DMA automatic data movement During the data reception process, the Timer captures a data edge every 2uS or 4uS, and then automatically triggers DMA, which automatically moves the data of the Timer register to the specified array in the RAM area. The entire data reception process does not require the participation of the CPU. With the existence of DMA, the CPU does not need to frequently interrupt to fetch data, nor does it need to worry about the loss of Timer capture register data. It only needs to focus on the decoding process. Figure 5. FM0 DMA mode decoding diagram Decoding process description: 1. Standby state: TimerA is configured in capture mode, TimerA interrupt is enabled, and wait for data to arrive 2. Capture the first data edge: Enable DMA in TimerA interrupt, enable TimerB and TimerB interrupt 3. Data reception: DMA automatically moves the subsequent data edges to the memory array; MCU decodes at the same time 4. Data end: TimerB determines the end of data reception 5. Decoding ends Figure 6. Program flow chart Actual test results: 120 bytes of data are used for FM0 decoding test, in which the data bits "1" and "0" each account for approximately 50%. After MSP430F5438 completes decoding, the data is output through the serial port as shown in Figure 7: Figure 7.Data received by the serial port For the 1Kbits data in the figure above, the measured MCU completes decoding, and the delay in receiving the data packet is about 220uS. As shown in Figure 8 Figure 8. Real-time decoding Using MSP430F5xx SPI and DMA to achieve FM0 encoding and transmission method ETC OBU system MCU uplink data rate is 512Kbps. Through the flexible application of on-chip DMA and SPI modules, FM0 data transmission can be easily completed
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