Application of MSP430F in ETC

　　TI's MSP430 microcontroller product series has a 16-bit RSIC architecture and ultra-low power consumption. As the latest product series of MSP430, F5xxx uses 0.18um process for the first time, and the current consumed by 1MIPs is as low as an astonishing 160uA, and the main frequency reaches 25MIPs. At the same time, MSP430F5xxx provides a wealth of on-chip functional modules, such as hardware RTC, 12-bit ADC, flexible clock system, hardware CRC16, power management module and multi-channel flexible and powerful DMA, supporting data exchange in standby mode.

　　Introduction to the Expressway Toll Collection System (ETC)

　　The non-stop toll collection system (also known as the Electronic Toll Collection System, or ETC system) is an intelligent transportation subsystem that uses RFID technology to realize automatic toll collection without stopping. The system automatically completes the toll collection process without the driver stopping or the toll collector operating, through the dedicated short-range communication between the road side unit (RSU) and the on-board electronic tag (OBU).

　　ETC on-board unit structure

Figure 1. ETC OBU structure diagram

　　As shown in Figure 1, OBU consists of a battery system, MCU, RF, display and card reader (ESAM card, CPU card, RF card). As the center of the entire system, MCU is responsible for managing display, card reading, and data processing and exchange with the RF part.

　　Introduction to FM0 encoding method

　　When the vehicle passes through the toll station, the OBU and RSU exchange data at high speed through 5.8G carrier modulation. The data is modulated using HDLC FM0. FM0 encoding follows the following three rules:

　　A. A level jump within a cycle indicates "0";

　　B. No level jump in a cycle represents "1";

　　C. The levels of two adjacent cycles are opposite.

　　Please refer to Figure 2 for data format

Figure 2. FM0 encoding method

　　The vehicle electronic tag system poses two challenges to the MCU: low power consumption and high-speed data communication capability.

　　The battery of the vehicle electronic tag is required to have a lifespan of more than 5 years or be able to support more than 10,000 transactions. The low power design of the entire system has become the primary task of engineers. Secondly, the baud rate of RSU to OBU downlink data reaches 256Kbps, and the baud rate of uplink data reaches 512Kbps. Since the vehicle travel time is very short, the OBU needs to respond quickly to the data and commands of the RSU. The maximum data packet can reach 1Kbits, and the OBU is not allowed to decode it after receiving the entire data packet, which requires the MCU to have real-time encoding and decoding capabilities. [page]

　　Generally, the soft decoding of FM0 needs to obtain the level width of the data to achieve decoding. There are usually two ways. One is that the Timer captures the data edge, and then the software determines the width between the data edges in the interrupt. The other is to sample the level of the data line at a fixed time and obtain the level width by counting. The ETC downlink data rate reaches 256Kbps. For data "0", the width between the data jump edges is only 2uS. For data "1", the data edge width is only 4uS. Taking the first method as an example, the traditional soft decoding process is as follows:

Figure 3. Timer capture interrupt mode

　　As shown in Figure 2, during the data reception process, the Timer will capture a data edge every 2uS or 4uS and save the data edge to the corresponding register. Therefore, the data in the Timer capture register will be updated at the fastest every 2uS. This requires the CPU speed to be fast enough to complete the decoding process within at least 2uS. Otherwise, the data in the Timer capture register will be overwritten by the new data, causing decoding errors. Assuming that the MCU needs 50 cycles to complete 1 bit decoding, then at least the MCU main frequency must reach 25MIPS to achieve real-time decoding. Usually, we will select MCUs with a main frequency of more than 40MIPs, and the power consumption of these high-speed MCUs is often difficult to meet the requirements of the ETC system. Therefore, many ETC manufacturers use a dual MCU approach, with a high-speed MCU to implement FM0 real-time encoding and decoding, and another low-power MCU, usually MSP430, to manage the power consumption of the entire system. This increases the cost and complexity of the system. The advent of MSP430F5xxx can simultaneously meet all the challenges of the ETC system to the MCU and solve the customer's troubles.

　　Method of using F5xxx on-chip DMA and TimerA capture function to implement FM0 real-time decoding

　　The excellent low power consumption characteristics of MSP430F5xxx can meet the low power consumption requirements of ETC OBU. As the latest product series of MSP430, F5xxx adopts 0.18um process for the first time, and the current consumed by 1MIPs is as low as 160uA. The on-chip PMM (power management module) allows users to flexibly adjust the core voltage according to the MCU load to ensure the lowest power consumption. In addition, it has multiple low power consumption states. In the typical LPM3 mode, the power consumption is only 2uA when the RTC is turned on and the RAM data is retained.

　　In addition to its excellent low power consumption, the MSP430F5xx can only reach a maximum frequency of 25MIPS, but due to its flexible multi-channel DMA, it can be linked with the Timer to achieve automatic data movement without interfering with the CPU, which greatly enhances the MCU's data throughput, making the main frequency no longer a bottleneck, and completing the near real-time decoding of FM0. In addition, the hardware CRC16 module allows the MCU to complete data verification by operating registers. The real-time decoding process using DMA and CRC16 is shown in Figure 4:

Figure 4. Decoding of DMA automatic data movement

　　During the data reception process, the Timer captures a data edge every 2uS or 4uS, which will automatically trigger DMA, and DMA will automatically move the data in the Timer register to the specified array in the RAM area. The entire data reception process does not require the participation of the CPU. With the existence of DMA, the CPU does not need to frequently enter and exit interrupts to fetch data, nor does it need to worry about the loss of the Timer capture register data. It only needs to focus on the decoding process.

Figure 5. FM0 DMA mode decoding diagram

　　Decoding process description:

　　1. Standby state: TimerA is configured in capture mode, TimerA interrupt is enabled, and waits for data to arrive.

　　2. Capture the first data edge: Enable DMA in TimerA interrupt, enable TimerB and TimerB interrupt

　　3. Data reception: DMA automatically moves the subsequent data to the memory array; at the same time, MCU decodes

　　4. Data end: TimerB determines the end of data reception

　　5. Decoding completed[page]

Figure 6. Program flow chart

　　Test results:

　　120 bytes of data are used for FM0 decoding test, in which data bits "1" and "0" account for about 50% each. After MSP430F5438 completes decoding, the data output through the serial port is shown in Figure 7:

Figure 7. Data received by the serial port

　　For the 1Kbits data in the figure above, the measured MCU completes decoding, and the delay in receiving the data packet is about 220uS. As shown in Figure 8

Figure 8. Decoding real-time performance

　　How to use MSP430F5xx SPI and DMA to implement FM0 encoding and transmission

　　The uplink data rate of the ETC OBU system MCU is 512Kbps. By flexibly applying the on-chip DMA and SPI modules, FM0 data transmission can be easily completed.