[RA] Renesas MCU power supply design +493420A

A low-power (24W) buck converter with adjustable output voltage and current based on the Renesas R7FA2E1A72DFL controller.
 
This design is a low-power buck converter (24W) with controllable voltage and current. It is
designed using the Renesas R7FA2E1A72DFL controller and uses Four peripheral control schemes: PWM, ADC, SPI, and GPIO
: ADC sampling of the output current and output voltage, and dual-loop PI control. The voltage loop is the outer loop and the current loop is the inner loop.
Interactive panel: imitates the Unilever adjustable power supply. Design, two rotary encoders adjust the output voltage and output current respectively, three of the four mute buttons are used to quickly switch output parameters, one is used for output enable, and an output enable indicator light.
 
Figure 1 Renesas MCU io setting diagram
 
Figure 2 Interactive panel front
 
Figure 3 Interactive panel back
 
Figure 4 Buck converter front
 
Figure 5 Buck converter back
 
design considerations:
The main design parameters of the buck converter are filter inductance and output filtering capacitance.
The calculation formula of the filter inductor in CCM operating mode is as follows.
In the formula, Vin and Vo are the input and output voltages, T is the switching period, Io is the rated output current, and 0.2 represents the inductor current ripple coefficient.
Calculation of the output filter capacitor in CCM operating mode The formula is as follows.
In the formula, ΔU represents the expected ripple voltage value, T is the switching period, Io is the rated output current, 0.2 represents the inductor current ripple coefficient, and 8 in the denominator is simplified and has no special meaning for

MOS tube selection . Several key parameters of the model: Qg, Coss, Vds.
Qg is the equivalent gate capacitance. This characteristic of the MOS tube determines the value of the bootstrap capacitor in the gate drive circuit;
Coss is the equivalent output capacitance. This characteristic of the MOS tube determines the value of the PWM dead zone;
Vds is the drain-source withstand voltage value. Considering the existence of parasitic inductance, a certain margin should be left in the selection of Vds;
in addition, the on-state resistance, thermal resistance, power dissipation, etc. of the MOS tube must be checked.
If you want to use the body diode of a MOS tube, you must also pay attention to the relevant parameters of its body diode.

 
Other random thoughts:
This design uses a 12V power adapter for power supply. The power supply for the gate driver is taken directly from the input voltage. If you need to increase the input voltage level, please provide 12V power supply for the gate driver.
The voltage sampling circuit and current sampling circuit of this design are preset with active RC filter circuits. If the ADC sampling waveform has many burrs, a low-pass filter of a certain frequency can be added, usually 16kHz, with a resistance of 10kΩ and a capacitance of 10kΩ. 1nF.
This design uses MOS tubes instead of rectifier diodes on the low side, and sets a reasonable PWM dead time to achieve ZVS turn-on of the lower tube and improve efficiency.
In this design, the input filter capacitor is placed close to the drain of the MOS tube to reduce parasitic inductance.
In this design, the filter inductor is placed close to the midpoint of the half-bridge to reduce the copper area of ​​the power node and reduce the antenna effect.
In this design, the digital ground and power ground are isolated, and only a single point connection is made for gate driving and signal sampling.
 
Figure 6 The current loop when the upper tube is turned on
 
Figure 7 The current loop when the lower tube is turned on
 
Figure 8 The current loop that will suddenly change (PCB layout requires extra attention)
 
Figures 6, 7, and 8 are quoted from: PCB Layout Techniques of Buck Converter [https ://fscdn.rohm.com/en/products/databook/applinote/ic/power/switching_regulator/converter_pcb_layout_appli-e.pdf]
 
When burning the program, the operation method of the chip entering the SCI serial port download mode:
pull down the RST pin, Pull the BOOT pin low, pull the RST pin high, and pull the BOOT pin high.
Also note that when installing Renesas' flash programmer tool, open it in administrator mode, otherwise an error will be reported.
For program writing, refer to the [RA2E1RA2L1 Getting Started Guide] in the attachment of this project.