EETalk: What pitfalls have you encountered during PCB design?

okhxyyo

EETalk: What pitfalls have you encountered during PCB design? [Copy link]

 

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Hello~ Everyone~ Let's chat together~ Recently, I saw several netizens in the forum asking questions about PCB design. Some of them encountered operation problems when using the software, and some said that because they were not familiar with some processes and details of PCB production technology, problems occurred in the design and production process of the board, and they had to rework and redo it, which cost more money~~

Our friends, have you ever encountered any pitfalls in the PCB design process?

Let’s talk about it, where are the pitfalls?

Also tell other friends which details they need to pay attention to in order to avoid pitfalls! ! ! ! !

大鹏roc

In which areas should we pay attention to which details to avoid pitfalls? ! ! ! !

秦天qintian0303

The most annoying pitfall is the virtual connection. It looks like it is connected, but it is not. You won’t know it unless you check for errors.

盛世辉煌电子科学

Safe distance

呜呼哀哉

The problem I encountered recently is the copper thickness. The default processing method for the inner layer of a four-layer board is 0.5OZ, and the overcurrent line width is calculated based on 1OZ. During processing, it was found that the price was different.

There is also the electrical clearance caused by the LQFPF package pin spacing set to 7mil, the routing clearance set to 10mil, and the line was not deleted cleanly when trying to route. There is an oblique dotted line on the pad, and the adjacent pin routing always reports a rule conflict. When not routing, the pad is normal again. I checked it for a long time at that time

dcexpert

Does this picture represent a design black hole?

殷成

During the design process, the power line was not made thick enough, resulting in insufficient overcurrent capacity.

okhxyyo

dcexpert posted on 2022-10-17 20:07 Does this picture represent a design black hole?

Hahahaha, my original intention was to trick.

okhxyyo

Alas, published on 2022-10-17 16:49 I recently encountered a problem with copper thickness. The default for the inner layer of a four-layer board is 0.5OZ. The overcurrent line width calculated based on 1OZ was found to be different during processing. ...

The line segment was not deleted cleanly and was blocked by the device. This is really painful. I have encountered this before and I also checked it for a long time.

okhxyyo

Qintianqintian0303 posted on 2022-10-17 15:39 The most annoying pitfall is the virtual connection. It looks like it is connected, but it is not. You won’t know it unless you check for errors

The PCB boards that come back from plate making should also be checked for this problem. I encountered this once before. The board had functional problems after it was taken out. After checking for a long time, I found that it was a process problem of the plate making factory. There was a short circuit somewhere on the board.

秦天qintian0303

okhxyyo posted on 2022-10-17 21:51 The PCB board that comes back from the plate making should also be checked for this problem. I encountered it once before. The board has always had problems with its functions. After checking for a long time, ...

I have made many experimental boards, and I did encounter a short circuit once. The driver had a broken code screen, and one of them could not light up no matter what. Later, I took all the parts off and found that the internal part was broken. This was the first time since I started working in this industry.

盛世辉煌电子科学

Safe distance of development board

kingweison