Analysis of the setting method of single chip interrupt priority

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Analysis of the setting method of single chip interrupt priority [Copy link]

Contains five interrupt sources, two levels of interrupt priority, and programmable priority settings, which can be set through IP:

　　Analysis of the setting method of 51 single-chip microcomputer interrupt priority:
　　PX0 (IP.0), external interrupt 0 priority setting bit;
　　PT0 (IP.1), timer/counter T0 priority setting bit;
　　PX1 (IP.2), external interrupt 0 priority setting bit;
　　PT1 (IP.3), timer/counter T1 priority setting bit;
　　PS (IP.4), serial port priority setting bit;
　　PT2 (IP.5), timer/counter T2 priority setting bit.
　

　　From this picture we can see:
　　EA is the interrupt control bit, EA=1 opens the interrupt, EA=0 masks the interrupt (manually set during programming).
　　So where is EA set? It is set in IE (interrupt enable register)

　　The seventh bit is EA, and the rest are the fourth bit ES, the third bit ET1, the second bit EX1, the first bit ET0 and the zeroth bit EX0. Can you see their shadows in the above picture? That's right, otherwise IE can be called the interrupt enable register? Doesn't it first set the total interrupt enable, and then set whether other interrupts are allowed? Next, let's look at other interrupt enable bits
　　ES: serial port interrupt open control bit, ES=1, respond to serial port interrupt, ES=0, disable serial port interrupt
　　ET1: T1 overflow interrupt open control bit, ET1=1, respond to interrupt generated by T1 overflow; ET1=0, disable interrupt generated by T1 overflow
　　EX1: external interrupt 1 open control bit, EX1=1, respond to external interrupt, EX1=0, disable external interrupt
　　ET0: function is the same as ET1, corresponding to T0
　　EX0: function is the same as EX1, corresponding to external interrupt 0
　　In this way, whether the interrupt is turned on or not is up to you, and you can directly control the corresponding interrupt and the total interrupt EA with whatever you want.
　　Now that we have turned on the interrupt, the CPU will detect whether the corresponding interrupt has arrived, so how to detect it? Next we will use a few other useful bits
　　

　　The seventh bit TF1, the fifth bit TF0, the third bit IE1, and the first bit IE0
　　　　of TCON. The first bit TI and the zeroth bit RI of SCON.
　　RI (SCON.0) is the serial port receive interrupt flag. When the serial port is allowed to receive data, RI is set by hardware after each serial frame is received. Note that RI must be cleared by software.
　　TI (SCON.1) is the serial port transmit interrupt flag. When the CPU writes a transmit data into the serial port transmit buffer, the transmit process is started. TI is set by hardware after each serial frame is sent. When the CPU responds to an interrupt, TI cannot be automatically cleared. TI must be cleared by software.
　　TF1: When the timing time of T1 is reached or when the count number is reached, the TF1 bit will be triggered, and then the CPU will detect the TF1 bit and execute the corresponding interrupt. After responding to the interrupt, the hardware will clear it.
　　TF0: corresponds to TF1
　　IE1: external interrupt request flag, external interrupt execution, request interrupt, corresponding to IE1=1, CPU responds to the interrupt, and the hardware clears IE1.
　　IE0: Corresponding to IE1
　　, but for external interrupts, there are two interrupt triggering modes, one is low level triggering, the other is falling edge triggering. We need to control differently for different situations, so how to select these two modes? We see that the second and zeroth bits of TCON are useless. The second bit IT1 corresponds to external interrupt 1, and the zeroth bit IT0 corresponds to external interrupt 0. If they are high level, they are falling edge triggered, and if they are low level, they are low level triggered.