CPU and peripherals of TMS320C6000 series DSP

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CPU and peripherals of TMS320C6000 series DSP [Copy link]

This book focuses on the internal structure of the TMS320C6000 series DSP and the development and use of peripheral devices. It can be used as a reference for program developers, system design engineers, etc. based on TI DSP, and can also be used as a reference book for elective courses for undergraduate and graduate students in related majors.

The TMS320C6000 series DSP is a high-performance digital signal processor launched by TI. Its processing core adopts a very long instruction word structure, and can execute up to 8 instructions in parallel in one instruction cycle. It integrates a large-capacity memory on the chip and adopts a secondary memory structure. It integrates a rich set of peripheral device interfaces on the chip. The powerful processing capability and rich on-chip resources make the TMS320C6000 series DSP higher in processing performance than other traditional DSPs.

This book focuses on the internal structure of the TMS320C6000 series DSP and the development and use of peripheral devices. The specific contents include: CPU data path and control, TMS320C620x/C670x internal program and data memory, TMS320C621x/C671x/C64x secondary internal memory, direct memory access register (DMA) controller, DMA and CPU data access performance, EDMA controller, host interface (HPI), expansion bus, PCI, external memory interface, boot mode and configuration, multi-channel buffered serial port, timer, interrupt selector and external interrupt, power saving logic, JTAG simulation design, general purpose input/output port (I/O).

This book can be used as a reference for programmers, system design engineers, etc. based on TIDSP, and can also be used as a reference book for elective courses for undergraduate and graduate students in related majors.

Book Catalog

Chapter 0 Introduction

0.1 Overview of TMS320 Series DSP

0.2 Application of TMS320C6000 Series DSP

0.3 Features and performance of TMS320C6000 series DSP

Chapter 1 TMS320C6000 Series DSP CPU Data Path and Control

1.1 Basic Structure of C6000 Series DSP

1.2 CPU General Register Group

1.3 Functional Units of Data Path

1.4 Register Crossing Path

1.5 Memory Access Path

1.6 Data Address Path

1.7 TMS320C6000 Control Registers

1.8 TMS320C67x Control Register Extension

1.9 TMS320C64x Control Register Extension

1.10 Extensions to the TMS320C64x Architecture

Chapter 2 TMS320C620x/C670x Internal Program and Data Memory

2.1 Program Memory Controller

2.2 Internal Program Memory

2.3 Data Memory Controller

2.4 Internal Data Memory

2.5 Peripheral Bus

Chapter 3 TMS320C621x/C671x/C64x Secondary Internal Memory

3.1 Overview

3.2 TMS320C621x/C671x/C64x Cache Definition

3.3 TMS320C621x/C671x Secondary Memory

3.4 TMS320C64x Secondary Memory

3.5 L1P Operation

3.6 L1D Operations

3.7 L2 Operation

3.8 Application-level optimization

3.9 Program-level optimization

3.10 Examples

Chapter 4 Direct Memory Access Register (DMA) Controller

Chapter 5 DMA and CPU Data Access Performance

Chapter 6 EDMA Controller

Chapter 7 Host Computer Interface (HPI)

Chapter 8 Expansion Bus

Chapter 9 PCI

Chapter 10 External Memory Interface

Chapter 11 Boot Modes and Configuration

Chapter 12 Multichannel Buffered Serial Ports

Chapter 13 Timer

Chapter 14 Interrupt Selector and External Interrupts

Chapter 15 Power Saving Logic

Chapter 16 JTAG Simulation Design

Chapter 17 General Input/Output (I/O)