Optimizing DSP Power Budget by Adjusting Voltage Regulators
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System-level power conservation and power budget optimization are key in many applications. For example, data center operators strive to control energy consumption, portable device designers seek to reduce current consumption to achieve longer battery life, and communications systems need to reduce operating temperature and improve stability. The main specifications for power supply design are currently focused on: 1) maximizing efficiency over the entire load current range; and 2) adaptively scaling the output voltage based on load needs. Using voltage identification (VID) to adjust the output voltage is one way to meet these needs. Of course, VID programmability has been widely used in DC/DC core voltage regulators for microprocessor applications, based on the well-known adaptive voltage scaling (AVS) specification from Intel and AMD. However, these VID controllers are based on a multi-phase buck topology with features specifically tailored around very high current requirements. DSPs, FPGAs, and ASICs now have similar capabilities to minimize power consumption based on device activity, power and clock domain configuration, operating mode, and operating temperature. While digital pulse-width modulator (PWM) controller solutions with VID support[1] are available to meet this need, there is also a need for digital output voltage regulation of the ubiquitous analog controlled point-of-load (POL) regulators. In the process, analog power supply implementations (perhaps already designed in or tested on the test bench) can be easily adjusted to meet system-level power budget and cost targets that would otherwise be unattainable. Digital Output Voltage Regulation Given the benefits of the above design goals, TI now offers a VID programmer[2] as an application specific standard product (ATSP). Figure 1 shows the LM10011[/url], which is designed to complement analog POL DC/DC solutions and includes a high-precision digitally programmable current digital-to-analog converter (IDAC) that supports mode-selectable 4-bit and 6-bit VID interfaces. The precise DC current at the IDAC_OUT pin is proportional to the 4-bit or 6-bit digital input word and is input to the feedback (FB) node of the output regulation loop. As the input word accumulates, the IDAC_OUT current can be reduced, thereby adjusting the output voltage set point higher based on the regulator feedback resistor. FB The node is typically held at a constant voltage by the error amplifier of an analog control loop. 102)]查看详情 [color=r gb(85, 85, 85)]Figure1: ConventionalPOLregulators are paired with currentDACsto form6bit digitalVIDinterface Of utmost importance in this implementation is the compatibility of the VID solution with the analog POL regulator design. The POL can effectively be deployed as a slave device to the DSP. The IDAC solution is designed to help DSPs and other digital loads realize their full power saving capabilities and reduce power consumption, such as in communications infrastructure applications. In practice, this VID solution is designed to work with any POL regulator to regulate the core voltage (VCORE) of VID-enabled processors such as the KeyStone multicore DSP [3]. DSP Core Power Supply Figure 2 is a schematic of a multicore DSP with core voltage CVDD provided by a synchronous buck POL regulator. The power stage includes a 15A voltage mode regulator, a 560nH inductor, and ceramic input and output filter capacitors [2]. The 6-bit VID command from the DSP helps regulate the output voltage VOUT based on the changing performance requirements of the DSP. ![]() Figure2: Powering a MulticoreDSP/SoC Platform with Core Voltage Rails Using a Synchronous Buck Regulator with VID Controlled Adjustability The system implementation shown in Figure 1 uses a 4-wire (VCNTL) interface for a 6-bit VID, allowing for higher resolution or finer granularity in VID operation. The IDAC_OUT current has a maximum full-scale range of 59.2μA (VID[5:0] = 000000b = code 0). In 6-bit mode, this provides 64 settings with a resolution of 940nA and an error accuracy of better than 1%. The output voltage is determined by the DSP to be between 0.7V and 1.103V. This is equivalent to a VOUT adjustment resolution of 403mV/63 or 6.4mV. Slew limiting prevents abrupt changes in the output. The VID deglitch filter provides noise immunity (effectively adding a small delay between the transition of the VID line and the subsequent change in the IDAC_OUT current). During startup before receiving a VID command, the IDAC_OUT current can assume one of 16 discrete levels depending on the RSET value. This allows the DSP's core voltage to power up at a variety of levels, achieving greater system flexibility and reliability. However, it is worth noting that the specific DSP Not all voltages or ranges may be supported. For example, for the KeyStone I DSP, the expected operating range is between codes 31 and 50 (0.905V to 1.020V) [4]. The supply voltage for the LM10011 in Figure 2 is derived from the input bus. Another option is to use a nominal 3.3V or 5V bias rail provided by the PWM controller or elsewhere in the system (if available). No level translator or glue logic is required between the DSP and the current DAC. Figure 3 is a more detailed description of the VID interface and the associated timing details. VCNTL[2:0] carries two bits of data for each VID code. VID at a low or high level selects the lower and upper bits, respectively, while VIDS at a high level also latches the VID command, initiating a current change at IDAC_OUT with a 40μs time constant. Each voltage adjustment therefore requires two header-stitched accesses from the DSP to the controller. The first access writes the lower three bits and the second access writes the upper three bits. 85)]Figure3:6-bit ModeVIDCommunication Timing Diagram Using the VID GUI software[5], the output voltage waveform at startup and the transient response following the high and low VID transitions can be recorded, as shown in Figure 4. The input voltage is 5.3V. As expected, the output voltage transition occurs on the rising edge of the VIDS signal. Figure4:a) Monotonous startup to preset value;b) VID-followingVID-switching31 dec-50 dec-31 dec output voltage. Conclusion In this article we have briefly explored the challenges associated with DSP power budget optimization and introduced a simple method to use a low-cost analog POL controller through a VID interface. The main design considerations and circuit implementation are included. This method is low in complexity and easy to use, suitable for power and BOM optimized applications, and can fully meet the ever-present time-to-market and cost constraints. Simplicity, accuracy and low cost are important design criteria. References
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