[i=s]This post was last edited by lpxv on 2014-5-28 15:49[/i] Self-introduction: I’m a handsome guy working in the Nuclear Magnetic Resonance Laboratory Building of University of Electronic Science an
Quickly master SDC (Synopsis Design Constraints) timing analysis : https://training.eeworld.com.cn/course/2076Timing analysis is a key factor for 65 nm and smaller process geometries. You should know
I initially posted a general post for discussion, but maybe everyone didn’t know where to start, so I will now discuss it separately.
Original post : https://en.eeworld.com/bbs/thread-292614-1-1.htmlN