The topic of the 2019 National College Student Electronic Technology Competition was released at 7:30 this morning on August 7.
Netizens who don’t know the title can look here:
Reference topics for th
[i=s]This post was last edited by Gen_X on 2021-4-30 21:04[/i]Condition: Arteli development board AT32F421
MCU clock 120Mz, ADC clock 10Mz (maximum 28MHz, with plenty of margin).
Input: ADC1 first cha
Can anyone tell me: I clearly placed the GND network mark when I drew the schematic, but there is no GND network mark in the network report or PCB? I wonder if anyone knows what the reason is? Thank y
When I was making CHIP-ON-LEAD products recently , I always got NSOP. Either the ball shape was not good or the line could not be hit . The machine I used was KNS. I hope you experts can give me some