Design of LCD driver circuit for smart phone based on PXA27x

The quality of LCD screen design is directly related to the overall performance of smartphones. However, there are many types of LCD screens, and engineers need to design for the timing matching, power requirements, and different characteristics of controllers of various screens. This article introduces the characteristics of the PXA27x internal integrated LCD controller, the driver implementation method, and the related power supply design, and puts forward electromagnetic compatibility design suggestions.

The global smart phone market is in a period of rapid growth. Market research company Gartner predicts that with the decline in demand for handheld computers, global smart phone sales will grow to 14 million units in 2004, a growth rate of 140%, and is expected to grow significantly to 45 million by 2007. Facing the growing smart phone market, various chip manufacturers have successively launched chip solutions with their own characteristics: For example, Freescale's iMX21 processor is embedded with multimedia acceleration technology and supports MPEG4 and H. 263; Intel PXA27xBulverde processor is embedded with MMX technology and SpeedStep power saving technology, supporting MPEG4, MP3 decoding and 4 million pixel camera. Multimedia applications have also become a highlight of the next generation of mobile phones. Watching movies, watching TV, playing games, etc. on mobile phones are the development trend of the next generation of mobile phones.

Intel PXA27x is a processor with good multimedia application effects. It can even enable end users to enjoy 3D gaming experience on mobile communication devices. The LCD screen design effect, which is called the eyes of smart phones, has undoubtedly become one of the most important factors for consumers to choose. The following is a detailed introduction to the design and implementation of LCD in smart phones based on PXA27x processors.

LCD screen design

The LCD hardware design circuit based on PXA27x processor is shown in the figure, which mainly consists of three parts: LCD controller, timing ICLZ9FC22 and liquid crystal display LCD.

The PXA27X processor integrates an LCD controller to support a variety of LCD screens, such as dual-scan passive matrix displays (DSTN-LCD) and thin-film transistor active matrix displays (TFT-LCD). The main features include: support for single or dual-scan display mode, embedded frame buffer, support for up to 8-bit passive dual-scan display mode, support for up to 18-bit pixels without embedded frame buffer single-screen display panel, support for up to 24-bit pixels with embedded frame buffer single-screen display panel.

The controller has three display types:

Passive color mode, supports 16777216 (24-bit) colors;

Active color mode, supports 16777216 (24-bit) colors;

Passive black and white mode, supports 256 (8-bit) grayscale levels.

The LCD controller supports display screens up to 800×600 pixels. However, in the frame memory, the bus width of the memory and the size of the pixel encoding data limit the size of the display screen that can be driven.

The frame and palette data can be stored in the embedded SRAM or external memory. The LCD DMA controller has a total of 7 DMA channels. Through the 5 DMA channels 0-4, the frame and palette data can be loaded into the 16×6?-bit input FIFO (first in first out). Through the internal system bus, DMA channel 5 can be used to store the pixel encoding data placed in the external frame memory or embedded SRAM to the relevant 16×6?-bit input FIFO. The LCD controller uses it as a pointer to index a small 4×24-bit wide palette and obtain 24-bit pixel color. DMA channel 6 is used to transmit command data, and the command data stored in the frame header of the external memory or the internal SRAM of the LCD panel is transmitted and stored in the 4×52-bit command FIFO.

Depending on the type of display screen to be connected, the LCD controller can be programmed into the corresponding working mode: when connected to a black and white screen, it can be configured into 4-bit or 8-bit mode; when connected to a passive color screen, there are 8-bit and 16-bit working modes; when connected to an active color screen, the controller can be configured into 12-bit, 16-bit and 18-bit working modes.

Our LCD screen design scheme selected the active color mode, using Sharp's 3.5-inch TFT active color LCD display LQ035Q7DB02, and using the 16-bit working mode, i.e. RGB565. Due to the wide variety of LCD screens for handheld devices and the inconsistent standards of various manufacturers, the PXA27X LCD controller cannot match the Sharp 3.5-inch screen in terms of data format and display timing. Therefore, it is necessary to select a timing control IC or use CPLD to map the data interface with different data formats. Here, our timing control IC uses LZ9FC22. [page]

The PXA27X LCD controller consists of the following pins:

LDD[15?0]: 16-bit data line, the data lines of R, G, and B chrominance signals are 5 bits, 5 bits, and 6 bits respectively;

L_PCLK: Pixelclock, used to send the data of each point into the shift register. The maximum clock can reach 52MHz.

L_LCLK: Line clock, used to indicate that a line of data has been transferred from the shift register to the display driver chip, and to increase the line pointer by 1. In the 16-bit TFT mode, it is the horizontal synchronization signal;

L_FCLK: frame clock, used to indicate the start of a frame of image and to place the row pointer on the first row of the display. In 16-bit TFT mode, it is the vertical synchronization signal;

L_BIAS: In 16-bit TFT mode, an output enable signal is used to indicate that the data signal is latched to the pin in synchronization with the clock signal.

In order to display a frame of image, the PXA27X LCD controller first stores the image data to be displayed in the frame buffer, then lets the DMA address register of the LCD controller point to the starting address of the frame buffer, and reads the data in the frame buffer to the input FIFO queue. Since the 16-bit mode is used in this design, there is no need to decode the data in the frame buffer, so the LCD controller does not process the data but directly sends it to the output FIFO, and the output FIFO then sends the data to the LZ9FC22 through the pin to drive the LCD display.

Power supply design for LCD related circuits

This LCD design involves several power supplies, including VSHD (+3.3V), VSHA (+5), VDD (+15V), and VEE (-10V), as well as +21.6V for the backlight. Each voltage has a tolerance range. The voltage ranges are as follows:

+3.3V(3.0~3.6);

+5V(4.5~5.5);

+15V(14.5~15.5);

-10V(-10.5~-9.5);

+21.6V(~24).

Except for the +21.6V voltage for the backlight, the power-on sequence of the remaining voltages is either switched on and off simultaneously, or in the order of VSHD→VSHA→VEE→VDD on and VDD→VEE→VSHA→VSHD off. This project is designed in a simultaneous manner, using LT1944-1 from Lingte Company to output three voltages, VSHA (+5V), VDD (+15V) and VEE (-10V), and can also be turned on or off simultaneously using the control pins of the IC.

Electromagnetic compatibility design

In the design, in order to maintain the integrity of LCD signal data and ensure the quality of the LCD screen output image, it is necessary to add some protection devices appropriately. At the same time, the wiring layout of the PCB is also a factor. When wiring, the LCD data line (i.e., RGB line) should be as short as possible, and the spacing between lines should be large enough, such as keeping at least twice the line width. It is relatively simple to add ESD/EMI protection devices on the LCD data line, and such devices are easy to find.