Samsung launches LPDDR5 - efficient read and write storage management technology

On February 12, 2020, Samsung released a new generation of flagship Galaxy S series phones, including S20, S20+, and S20 Ultra. At the same time, it launched the industry's first LPDDR5 memory! According to Samsung's official microblog, compared with LPDDR4x, Samsung's LPDDR5 memory bandwidth is increased by 29%. At the same working speed, LPDDR5 saves 14% of power consumption compared to LPDDR4x!

A memory with such powerful performance and fast read and write speed must be able to effectively manage the write clock and read clock. LPDDR memory chips are usually used as memory materials. Such low-power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM) memory devices can usually be used in various types of electronic devices (smart phones, tablet personal computers (PCs), etc.).

In the LPDDR specification, a memory device may receive a write clock synchronized with write data from a memory controller, or may provide a read clock synchronized with read data to the memory controller, and a memory system of such a memory device may need to effectively manage duty cycle errors of the write clock and the read clock.

How to effectively manage this duty cycle error? On January 2, 2019, Samsung applied for an invention patent titled "Memory device for adjusting duty cycle and memory system having a memory device" (application number: 201910001529.8), and the applicant is Samsung Electronics Co., Ltd.

Based on the currently disclosed patent materials, let's take a look at how this memory improves the duty cycle.

As shown in the figure above, it is a block diagram of the memory system of the memory device of the invention of the patent, and the memory system 10 may include a memory controller 100 and a memory device 200. The memory controller is implemented by a system on chip (SoC), an application processor (AP), a mobile AP, a chipset or a group of chips, for example, it may be a semiconductor device that performs a memory control function, or a component included in the AP; the memory device is implemented by a volatile memory device, for example, a volatile memory device is implemented using RAM, dynamic RAM (DRAM) or static RAM (SRAM), or it may be implemented using DDR or LPDDR with better performance.

The memory controller includes a duty cycle controller 110, a duty cycle regulator 210 and a duty cycle monitor 220. The duty cycle regulator may also be referred to as a duty cycle executor. The memory device includes various components for storage operations such as data writing and reading, such as a memory cell array and its peripheral circuits.

So how is the division of labor between the memory controller and the memory device performed? The memory controller provides the clock signal for data write and read operations to the memory device. Since the memory device receives the write data DQ by using the clock signal received from the memory controller, the clock signal can be called the write clock WCK. Therefore, an internal write clock can be generated and used during the reception or output of the actual data DQ.

At this time, the operation of monitoring the duty cycle of the write clock WCK may correspond to the operation of monitoring the duty cycle of the clock signal applied to each node in the memory device. For example, during the data write operation, the memory device may receive the write data DQ and the write clock WCK together in synchronization with the write clock WCK, and the data receiver in the memory device may receive or latch the write data DQ by using the write clock WCK. Thus, the requirement of flexibly managing the duty cycle error is achieved.

As shown in the figure above, it is a flow chart of a method for operating a memory device. First, the memory device can communicate with a memory controller, and can receive write data and a write clock synchronized with the write data, and a write command from the memory controller. The memory device may include a data receiver and a write clock receiver, and the data receiver may receive the write data in synchronization with the write clock sent to the memory device.

Secondly, the duty cycle monitor can monitor the duty cycle of the write clock output by the write clock receiver, for example, the write clock can be sent via various paths within the memory device, and the duty cycle monitor can receive the write clock from nodes of one or more paths. Then, the duty cycle monitor can generate monitoring information having a digital value, and the monitoring information can be sent to the memory controller.

Finally, the memory device may receive a duty cycle control signal from the memory controller, and a duty cycle adjuster within the memory device may adjust the duty cycle of the write clock in response to the duty cycle control signal.

Next, let’s take a look at how the duty cycle controller and duty cycle monitor coordinate to complete the above tasks.

As shown in the above figure, which is a block diagram of a memory controller in a memory system, the memory controller 410 may include a duty cycle controller 411 and a duty cycle monitor 412. The duty cycle controller may output a first duty cycle control signal Ctrl_W for adjusting the duty cycle of the write clock WCK, and a second duty cycle control signal Ctrl_R for adjusting the duty cycle of the read clock RDQS.

The memory controller may receive the read data DQ and the read clock RDQS synchronized with the read data DQ from the memory device 420, and may latch the read data DQ in synchronization with the read clock RDQS. The duty cycle controller may generate a second duty cycle control signal Ctrl_R by using the second monitoring information D_Info_R from the memory device and the third monitoring information Res_Mor from the duty cycle monitor.

Through the mutual signal transmission between the duty cycle controller and the duty cycle monitor, the signal sending rhythm of the duty cycle controller can be monitored in real time, so that the duty cycle control can be completed accurately and the duty cycle error can be reduced.

The above is the memory duty cycle adjustment device and system invented by Samsung. Through reasonable design and intelligent solutions, the controller, monitor and regulator cooperate with each other to reduce the duty cycle error and improve system performance. Samsung's position in the memory industry can be said to be unshakable. Its LPDDR technology research and development and production have always been at the world's first-class level. It is for this reason that products and technologies promote each other and can continue to move forward!

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