High-speed DAC

928083047

The high-speed DAC output rate is 10Gsps, and the data line has 8 pairs of differential lines. When drawing the PCB, the differential pairs are made of equal length. Why is it not required that the pairs be made of equal length lines? ? ?

不足论

Yes, why not?

qwqwqw2088

If someone doesn't ask, ask him why.

chunyang

Generally speaking, if these data line pairs are independent of each other, that is, output to different target devices (a single chip has multiple independent functional subsystems, and each subsystem is regarded as an independent target), it is obvious that the equal length of the line pairs is meaningless. If they are non-independent and are part of a complete data transmission link, they obviously require equal length. The original poster's question involves DAC, but no specific information is provided, so it is hard to say.

928083047

chunyang posted on 2019-11-26 16:48 Generally speaking, if these data line pairs are independent of each other, that is, output to different target devices (a single chip has multiple independent functional subsystems, each...

It is the data line output from the FPGA end to the DAC chip; the GTX serial data line protocol is a single lane that transmits data independently, which is different from the ordinary LVDS differential. Ordinary LVDS data is multiple groups of lines that transmit a sampling point data, so it must be strictly equal in length to the accompanying clock. The working principle of GTX is that both single lane transmission and multiple lane transmission receive data serially and then frame it, so high-speed interfaces such as GTX do not need to be of equal length, and general ultra-high-speed lines should not be wound.