10 Mbps/100 Mbps/1000 Mbps Dual-Channel, Low-Power Industrial Ethernet PHY

Evaluation and Design Support

• Circuit Evaluation Board

• CN-0506 Circuit Evaluation Board (EVAL-CN0506-FMCZ)

• Design and Integration Documentation

• Schematics, layout files, bill of materials

Circuit Function and Advantages

The circuit shown in Figure 1 is a dual-channel, low latency, low power Ethernet physical layer (PHY) card that supports 10 Mbps, 100 Mbps, and 1000 Mbps speeds for Industrial Ethernet applications using linear and ring network topologies.

The dual channels support linear and ring network topologies commonly used in industrial sensing, control, and distributed control systems. The ADIN1300 Ethernet PHY has been extensively tested for electromagnetic compatibility (EMC) and electrostatic discharge (ESD) robustness and supports auto-negotiation to link with remote PHY devices at the highest advertised common speed. IEEE 1588 timestamping in the PHY reduces timing uncertainty in real-time applications and enhances link loss detection for redundant and real-time applications.

The circuit consists of two independent 10 Mbps, 100 Mbps, and 1000 Mbps PHYs, each with an Energy Efficient Ethernet (EEE) PHY core and all associated common analog circuitry, input and output clock buffers, management interfaces, subsystem registers, media access control (MAC) interface, and control logic.

The design is powered by the host field programmable gate array (FPGA) mezzanine card (FMC) development board, eliminating the need for an external power supply. The software programmable clock supports media independent interface (MII), reduced MII (RMII), and reduced gigabit MII (RGMII) MAC interface modes. The RJ45 port with integrated magnetics makes the solution as compact as possible.

The solution supports cable lengths up to 150 meters at Gigabit speeds and up to 180 meters at 100 Mbps or 10 Mbps. This solution is typically used in ring or bus topologies. The auto-negotiation feature of the ADIN1300 allows connection to other PHY devices at the highest supported speed.

Figure 1. EVAL-CN0506-FMCZ Simplified Block Diagram (Decoupling and All Connections Not Shown)

Circuit Description

Ethernet

Ethernet is the most common type of packet-based physical connection for data networking applications in local area networks (LANs), defined by multiple sections and specifications of the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard.

Ethernet is available in different speeds and transmission media. However, this circuit note focuses on 10BASE-T, 100BASE-TX, and 1000BASE-T over straight-through or crossover, Category 5e (CAT5e) or Category 6 (CAT6) twisted-pair cabling.

Linear and ring network topologies

Typical industrial Ethernet networks are deployed in linear or ring topologies. Compared to star networks, linear and ring network topologies have shorter cabling lengths, and ring networks also have a redundant path (see Figure 2). Each device connected to a linear or ring network requires two Ethernet ports to pass Ethernet frames along the network.

Figure 2. Linear and ring topologies

PHY

The PHY is a physical interface transceiver that implements the physical layer functions of the Open Systems Interconnection (OSI) model. The PHY encodes and decodes the data sent and received between devices, maintaining the integrity of frames and packets (see Figure 3).

PHY Hardware Configuration—Bonding Resistors

The ADIN1300 can be configured to power up ready to establish a link. This PHY hardware configuration uses external bonding resistors to provide a known configuration for power-up operation in unmanaged applications. In unmanaged applications, the user typically does not configure the PHY on the management data input output (MDIO). Instead, unmanaged applications rely on the PHY hardware configuration to start the ADIN1300 with the appropriate configuration, ready to link with the remote PHY partner. When the ADIN1300 is powered up, the hardware bonding pins are sampled when the device comes out of reset so that the PHY device knows how to configure the various functions.

The hardware configuration modes that this circuit note focuses on are speed, PHY address, automatic medium dependent interface crossover (Auto-MDIX), and MAC interface. The EVAL-CN0506-FMCZ contains resistors of various sizes to support various combinations and has a specific default configuration. If you need to change the default hardware configuration, you can insert or remove resistor components.

For more information on using other features and functions such as Energy Efficient Ethernet (EEE), energy detect shutdown, shutdown speed, and software shutdown, see the ADIN1300 data sheet.

Figure 3. Typical network sensor with PHY device

Physical layer—MAC interface

The MAC interface is the wired medium on the CN-0506. There are three MAC interface options: RGMII, RMII, or MII. RGMII supports all speeds up to 1000 Mbps, while MII and RMII support 10 Mbps and 100 Mbps, respectively. RGMII is the default interface for the CN0506.

There are two ways to select which MAC interface to use: by hardware bonding external resistors, or by using software register configuration. MACIF_SEL0 and MACIF_SEL1 are multifunction pins within the ADIN1300 (see the ADIN1300 data sheet for more information). For the CN-0506, the MACIF_SEL0 and MACIF_SEL1 pins can be configured according to Table 1 to select the MAC interface. Note that the MACIF_SEL0 and MACIF_SEL1 pins have weak pull-down resistors internally. Therefore, if there are no external bonding resistors, the default MAC interface is RGMII with a 2 ns delay.

Table 1. MAC interface selection

In this circuit note, the MAC interface selection is done through software configuration, using the GE_RGMII_CFG and GE_RMII_CFG registers in the ADIN1300. If the user prefers to configure the MAC interface in hardware, space is provided on the board for external pull-up and pull-down resistors. However, since the resistors are not installed, the PHY on the EVAL-CN0506-FMCZ powers up with the default RGMII interface.

PHY Address

There are four PHY address pins (PHYAD_x) that allow the user to configure the PHY to any of 16 PHY addresses. PHY addressing enables the system to have up to 16 independently controllable channels from a single controller.

The EVAL-CN0506-FMCZ is currently hardwired to a specific address, but this can be changed by changing the configuration resistors for each channel. Channel 1 is currently assigned address 0001 and Channel 2 is currently assigned address 0010.

Programmable MAC interface clock

The ADIN1300 has three MAC interface options: MII, RMII, or RGMII. For the RGMII and MII interfaces, the ADIN1300 requires a 25 MHz clock, while the RMII requires an external 50 MHz clock. In the user application, the user can choose to place a 25 MHz crystal near the XTAL_I and XTAL_O pins, or for the case of using RMII, the host controller, MAC interface, or switch chip can directly provide the required 50 MHz clock to the PHY.

The EVAL-CN0506-FMCZ includes two I2C programmable clocks (Y1 and Y2) from 100 kHz to 125 MHz to support the corresponding clock requirements of different MAC interfaces of the ADIN1300.

By default, the clock of each channel is set to 25 MHz at power-up. When using the RMII MAC interface, the clock can be programmed to 50 MHz.

Both clocks have the same I2C address, but by using the I2C address translator, the LTC4316, these clocks can be individually programmed to different addresses from each other. The LTC4316 XORs the incoming address, converting each incoming bit into a user-configurable conversion byte set by the chip's resistor divider network.

MDI Interface—Integrated Magnetics

Typically, the MDI interface connects the ADIN1300 to the Ethernet network through a transformer and an RJ45 connector. The CN-0506 uses an RJ45 connector with integrated magnetics. The integrated magnetics in the RJ45 connector generally provide improved electromagnetic interference (EMI) shielding and are smaller in size, requiring shorter trace routing than using discrete magnetics.

Integrated magnetic components include RJ45 connector, common mode choke, isolation transformer, LED, decoupling capacitors and termination resistors. The design may choose to use discrete magnetic components due to different overvoltage requirements in the design or if a specific EMI requires a different layout.

power supply

To reduce the number of power supplies, the analog circuit power supplies for the ADIN1300, MDIO, and MAC interfaces are taken from the 3.3 V rail of the FPGA through ferrite beads to reduce the noise entering the system.

The digital core of the ADIN1300 requires a 0.9 V supply. This power is derived on-board from the 3.3 V rail using an LT3502 pulse width modulation (PWM) step-down dc-to-dc converter; the converter converts the FPGA's 3.3 V supply to 0.9 V, consuming a maximum of 0.45 W of carrier power.

Software Overview

The FPGA reference design provided for use with CN-0506 configures each ADIN1300 independently. Each PHY (ADIN1300) is connected to a specified MAC interface, and three interface modes are supported between the ADIN1300 and the FPGA: RGMII, MII, and RMII.

Each mode has a separate hardware design language (HDL) because some modes require converters, such as Gigabit MII (GMII) to RGMII. The operating mode must be selected in the HDL to match the mode the user wants to use in Linux.

The EVAL-CN0506-FMCZ connects to a standard low pin count (LPC) FMC connector, and the software design is portable to many different FPGA development boards.

The supported Linux device trees for different modes and carrier combinations can be found on the CN0506 HDL page. For more information on Analog Devices standard Linux images, see the FPGA Image User Guide.