Design of DSP off-chip high-speed massive SDRAM storage system

In high-speed signal processing applications such as digital image processing and aerospace, strong support of high-speed and large-capacity storage space is required to meet the system's requirements for massive data throughput. Embedded DSPs are expanded by using large-capacity synchronous dynamic RAM (SDRAM). The system storage space method uses the ISSI company's IS42S16400 high-speed SDRAM chip, and the specific implementation of this design method in a digital signal processing system based on TMS320C6201 (referred to as C6201) is discussed in detail.

　　1 Introduction to IS42S16400 chip

　　IS42S16400 is a 16-bit word-wide high-speed SDRAM chip with a single-chip storage capacity of up to 64Mb (8MB) launched by ISSI. The main features of SDRAM are: ① synchronous access, read and write operations require a clock; ② dynamic storage, the chip needs to be refreshed regularly. IS42S16400 uses CMOS technology. Its synchronous interface and fully pipelined internal structure enable it to have a huge data transfer rate and can operate at a clock frequency of up to 133MHz, with a refresh frequency of 4096 times every 64ms. There are 4 memory banks inside the SDRAM chip. Through the row and column address time-division multiplexing system address bus, specific memory cells of different pages in different memory banks can be read and written to access and address. Before performing a read operation, the corresponding memory bank in the SDRAM must be activated in advance, a certain row of the memory must be selected, and then the column address must be entered to read the required data. There is an access delay between outputting the column address and returning the corresponding data from SDRAM. If you access a new page, you need to close all memory banks first, otherwise the opened page will always be valid. Before the write operation, since the relevant row address has been pre-activated, the data can be output while the column address is output, without delay. IS42S16400 provides a self-refresh mode setting, which allows the chip to run in a low-power state, thereby greatly reducing the power consumption of embedded systems.

　　2 External memory interface between C6201 and SDRAM

　　When the DSP chip accesses off-chip memory, it must pass the external memory interface EMIF (External Memory Interface). The EMIF of the C6000 series DSPs has strong interface capabilities, not only has a high data throughput rate (up to 1200MB/s), but also can directly interface with almost all types of memory currently available. In the C6201 system, four independent external memory interfaces (CEx) are provided. Except for the CE1 space, which only supports asynchronous interfaces, all external CEx spaces support direct interfaces to SDRAM. Table 1 summarizes the EMIF-compatible SDRAM configurations for C620X DSPs. Table 2 shows the SDRAM control commands supported by EMIF of C6000 series DSPs.

　　2.1 SDRAM refresh

　　In order to increase storage capacity, SDRAM uses silicon capacitors to store information. As time goes by, the capacitor must be recharged to maintain the data information in the capacitor. This is the so-called "refresh". Its existence also makes the application of SDRAM slightly complicated and brings a certain application difficulty.

　　C6000 series DSPs have special SDRAM control register (SDTCL) and SDRAM timing control register (SDTIM), which are used to control various timings of SDRAM, which greatly reduces the development difficulty of designers. The RFEN bit in the SDCTL register controls whether it is controlled by EMIF Complete the refresh of SDRAM. If RFEN = 1, EMIF will control the issuance of refresh commands (REFR) to all SDRAM spaces; and the PERIOD bit field in the SDTIM register controls the specific refresh cycle.

　　Before the REFR command, a DCAB command will be automatically inserted to ensure that all SDRAM is in an inactive state during the refresh process. After the DCAB command, EMIF starts to refresh regularly according to the value set by the PERD field in the SDTIM register. Before and after refreshing, the page information will become invalid.

　　For C620X, there is a 2-bit counter inside the EMIF SDRAM control module to monitor the number of refresh applications submitted. Each time an application is submitted, the counter increases by 1; after each refresh cycle, the counter decreases by 1. When reset, the counter is automatically set to 11b to ensure that it is refreshed several times before accessing. The counter is automatically set to 11b, which represents the emergency refresh state. At this time, the page information register becomes invalid, forcing the controller to close the current SDRAM page. Then, the EMIF SDRAM controller executes three REFR commands after the DCAB command to reduce the counter value to 0, and then continues to complete the remaining access operations.

　　2.2 Initialization of SDRAM

　　When a CE space is configured as an SDRAM space, it must be initialized first. Users do not need to control every step of initialization. They only need to write 1 to the INIT bit of the EMIF SDCTL register to apply for initialization of SDRAM. Then, EMIF will automatically complete the required steps. Initialization operations cannot be performed during SDRAM access. The entire initialization process includes the following steps:

　　①Issue the DCAB command to all SDRAM spaces;

　　②Execute 3 REFR commands;

　　③Issue the MRS command to all SDRAM spaces.

　　2.3 Page boundary control

　　SDRAM is a paging memory. EMIF's SDRAM controller will monitor the row address when accessing SDRAM to avoid row out of bounds when accessing. In order to accomplish this task, EMIF has four page registers internally, which automatically saves the address of the currently opened row and then compares it with the address of subsequent accesses. It should be noted that the end of the current access operation will not cause the activated rows in the SDRAM to be closed immediately. The control principle of EMIF is to maintain the current open state unless it must be closed. The advantage of this is that it can reduce the command switching time between closing/reopening, allowing the interface to fully utilize address information in the control process of memory access.

　　For C620X, each CE space contains 1 page register (only valid for SDRAM space configured), so C620X can only activate 1 page per CE space at a time. The number of address bits compared depends on the value of the SDWID bit in the SDCTL register. If SDWID = 0, the page size of the CE space is 512, and the compared logical address is bits 23 to 11; if SDWID = 1, the size of the CE space SDRAM page is 256, and the compared logical address is bits 23 to 10 . Once it is discovered that a page out-of-bounds access occurs, EMIF will automatically perform a DCAB operation and then start a new row access.

　　2.4 Shift of access address

　　Since the SDRAM row logical address and column logical address multiplex the same EMIF pin, the EMIF interface needs to perform corresponding shifting processing on the row address and column address. The shifting of addresses is controlled by the SDWID bit in the SDCRL register.

　　In addition, for SDRAM, because the input address is also a control signal, the following points need to be explained:

　　①The high-order address signal during the validity period of RAS will be latched by the EMIF internal SDRAM controller to ensure that the correct bank is selected when executing the READ and WRT commands;

　　②During the READ/WRT operation, EMIF will keep the pre-charge signal low (C620X is SDA10) to prevent the auto-pre-charge operation from occurring after the READ/WRT command is executed.

　　2.5 Design of interface timing

　　For C620X, the interface timing between EMIF and SDRAM is controlled by the SDCTL register. EMIF provides 5 timing parameters, 3 of which are set in the SDCTL register, and the other 2 are fixed values, as listed in Table 3. When analyzing the coordination of the interface timing, it is necessary to calculate the size of the "rich time" tmargin. This is a margin in timing obtained after considering the worst case scenario provided by the device manual of the SDRAM chip. As for the size of the tmargin value , is an issue that needs to be considered by the system design layer. The specific requirements vary with different systems, and are closely related to the actual wiring conditions of the printed board and the load conditions.

　　3 Application of IS42S16400 chip in system design

　　3.1 Interface implementation between C6201 and IS42S16400

　　Since the IS42S16400 is a 64Mb SDRAM chip with a 16-bit word width, and the EMIF of the C6201 only provides a synchronous external storage interface with a 32-bit word width, in order to keep the storage space of the entire system continuous, 2 SDRAM and DSP chips are used to form an actual size of 16MB external storage system, as shown in Figure 1. The meanings of the pins of the IS42S16400 chip in Figure 1 are as follows: CS, chip select; CLK, system synchronization clock; RAS, row address selection; CAS, column address selection; WE, read/write enable; CKE, clock enable, DQMU, DQML, high and low byte enable; A[13:12], Bank address selection line; A[11:0] row and column address first; DQ[15:0], bidirectional data port.

　　As can be seen from Figure 1, although C6201 provides 32-bit address addressing capability, the address signal directly output by EMIF is only EA[21:2]. Under normal circumstances, the EA2 signal corresponds to the logical address A2, but this does not mean that the DSP chip can only access words (32 bits) when accessing external memory. The lowest 2 to 3 bits of the actual internal 32-bit address are decoded. Output by BEx can control byte access. The higher logical address is decoded and outputs CE[3:0].

　　In the actual system implementation, the CLKOUT1 clock frequency of C6201 is 200MHz, so the actual operating frequency of SDRAM is 100MHz, (SDCLK=CLKOUT2=CLKOUT1 frequency/2), that is, tcyc=10ns. SDRAM is configured in CE2 space (starting logical address is 0x02000000).

　　3.2 C6201 EMIF SDRAM register setting

　　Table 4 lists the EMIF register names and corresponding bits or bit fields that need to be set to configure SDRAM.

　　The SDCEN bit (bit 6) in the EMIF global control register is set to 1 to enable the output of the SDRAM synchronization clock SDCLK. The MTYPE bit field (bits 6~4) in the EMIFEC2 space control register is set to 011b, which is used to configure CE2 as a 32-bit wide SDRAM space. It can be found from the IS42S16400 data sheet that tRC=70ns, tRP=18ns, tRCD=18ns, so the TRC bit field (bits 15~12) in the EMIF SDRAM control register should be set to 0110b, and the TRP bit field (bits 19~16) should be Set to 0001b, the TRCD bit field (bits 23 to 20) should be set to 0001b. The INIT bit (bit 24) is set to 1 to force power-on initialization of the SDRAM. The RFEN bit (bit 25) is set to 1 to enable EMIF to refresh the SDRAM. The SDWID bit (bit 26) is set to 1 to indicate to EMIF that the word width of the SDRAM chip used is 16 bits. Since the refresh frequency of IS42S16400 is 4096 times every 64ms, according to the formula PERIOD=trefresh/tcyc, EMIF SDRAM timing control register The PERIOD bit field (bits 11~0) in is set to 0x61A.

　　3.3 SDRAM configuration program source code in CCS development environment

　　In TI's integrated development environment CCS (Code Composer Studio), the configuration program C code of the IS42S16400SDRAM chip is as follows:

　　#include＜emif.h＞…/＊Other user programs＊/ /＊Read the default settings of the EMIF control register＊/
　
　　unsigned int g_ctrl=GET_REG (EMIF_GCTRL);

　　unsigned int ce0_ctrl=GET_REG(EMIF_CE0_CTRL);

　　unsigned int ce1_ctrl=GET_REG(EMIF_CE1_CTRL);

　　unsigned int ce2_ctrl=GET_REG(EMIF_CE2_CTRL);

　　unsigned int ce3_ctrl=GET_REG(EMIF_CE3_CTRL);

　　unsigned int sdram_ctrl=GET_REG(EMIF_SDRAM_CTRL);

　　unsigned int sdram_ref=GET_REG(EMIF_SDRAM_REF);

　　/*EMIF global control register - enable SDCLK*/

　　SET_BIT(&g_ctrl,SDCEN);

　　/*Set CE2 as SDRAM space*/

　　LOAD_FIELD(&ce2_ctrl, MTYPE_23SDRAM, MTYPE, MTYPE_SZ);

　　/*Set SDRAM control register*/

　　LOAD_FIELD(&sdram_ctrl,6,TRC,TRC_SZ);

　　LOAD_FIELD(&sdram_ctrl,1,TRP,TRP_SZ);

　　LOAD_FIELD(&sdram_ctrl,1,TRCD,TRCD_SZ);

　　SET_BIT(&sdrrm_ctrl,SDWID);

　　SET_BIT(&sdrrm_ctrl, INIT);

　　SET_BIT(&sdrrm_ctrl, RFEN);

　　/*Set the refresh cycle of SDRAM*/

　　LOAD_FIELD(&sdram_ref,0x61A,PERIOD,PERIOD_SZ);

　　/*Reconfigure EMIF control register*/

　　emif_inif(g_ctrl, ce0_ctrl, cel_ctrl, ce2_ctrl, ce3_ctrl, sdram_ctrl, sdram_ref);

　　…/＊Other user programs＊/

　　Conclusion

　　The above introduces the specific hardware interface implementation of TMS320C6201 DSP chip and SDRAM (IS42S16400). Due to the advantages of large capacity, high speed and low price of SDRAM, using SDRAM to build a mass storage system for embedded applications will become an effective method. At present, the system has been debugged. Using SDRAM as an external high-speed, large-capacity main memory for DSP systems has very obvious advantages, which fully demonstrates the good application prospects of SDRAM in embedded systems.