Design of Chirp Signal Source Based on DSP Builder

DSP Builder is a system-level (or algorithm-level) design tool provided by Ahera. It is built on multiple software tools and connects the design tools in the two design fields of system level (algorithm simulation modeling) and RTL level (hardware implementation), maximizing the advantages of the two tools. DSP Builder can help designers complete DSP design based on FP-GA. In addition to graphical system modeling, DSPBuilder can also automatically complete most of the design process and simulation until the design file is downloaded to the DSP development board. This design uses the DSPBuilder development tool to first implement a direct digital synthesis (DDS) module with controllable output frequency variation; then, according to the variation law of the Chirp function, the output frequency variation law of the DDS is controlled.

1 General characteristics of Chirp function

During the transmission process, electromagnetic waves will pass through dispersive media, such as inhomogeneous waveguides, and will undergo dispersion in the high-altitude ionosphere. The Chirp function plays an important role in the de-dispersion processing of radio astronomical signals. The study of implementing the Chirp function in FPGA is an important part of FPGA-based radio cosmic signal processing, as shown in Figure 1.

According to the corresponding variation law between the output frequency and the current sampling time, the Chirp function is generally divided into two types: linear Chirp function and nonlinear Chirp function. Figure 2 and Figure 3 are the performance diagrams of the two Chirp functions in the frequency domain.

As can be seen from Figure 2 and Figure 3, the relationship between the frequency output and time ft of the Chirp function can be summarized as follows: For a linear Chirp function, there is a relationship in the continuous domain and time domain:

Where: k is a constant; f0 is the initial output frequency; t is the continuous time.

In the discrete time domain, there is a relationship:

Where: k is a constant; f0 is the initial output frequency; n is the sampling point.

For the nonlinear Chirp function, there is a relationship in the continuous domain and time domain:

Where: f(t) is a nonlinear function; f0 is the initial output frequency; t is the continuous time.

In the discrete time domain, there is a relationship:

Where: f(n) is a nonlinear function; f0 is the initial output frequency; n is the sampling point.

2 Design of DDS module

The working principle of the digital frequency synthesizer (DDS) module is: divide the sine function value of 0~2π into N parts, store the amplitude value of each point in ROM, and then use a phase accumulator to accumulate the phase value ωT each time to obtain the current phase value, and obtain the current amplitude value by searching ROM. The system block diagram is shown in Figure 4.

The main parameters of DDS include: system clock frequency, frequency control word length, frequency resolution, number of ROM units, and ROM word length. The DDS designed is 10 bits, and the clock frequency is the input clock frequency after conversion to the VHDL file. This is a very flexible input frequency. Here, it is assumed that the input frequency is fin, the frequency control word length is 16 bits, the number of ROM units is 210, the ROM word length is 9 bits, and the frequency resolution is:

Where: fc is the system clock frequency.

The frequency control word is:

Where: f is the frequency to be synthesized; T is the system clock. It can be seen that when the input frequency control word changes, the output frequency fout also changes accordingly. The design from DDS to Chirp signal source is based on this idea, as shown in Figure 5.

Among them, input port 1 is the initial phase control word input terminal, and its input value determines the initial output phase of the signal source. Input port 2 is the frequency control word FTW input terminal. If different frequency control word values ​​are written to this input terminal, different output frequencies can be obtained at the output port. Input port 3 is the initial frequency control word input terminal, and its input value determines the initial bias frequency of the signal source.

LUT is a sine data lookup table module (Look Up Table). According to the algorithm of DSP Builder, a complete sine wave cycle is sampled 1 024 times and stored in LUT. In Matlab, set Matlab array: 511*sin([0:2*pi／(2^10):2*pi]), the left input end is the address input end of the search data, and the right output end is the discrete sine wave signal output end.

The first parallel adder module (Parallel Adder Subtrac-tor) is used as a phase accumulator. The bus structure (AltBus) module provided by Altera determines that the length of the accumulator is 16 bits, that is, the maximum output range of the accumulator is 216, thereby determining formula (5).

The second parallel accumulator module (Parallel Adder Subtractor1) serves as an initial phase offset accumulator, which adds the initial phase control word and the frequency control word to provide an initial offset phase for the output frequency.

The third parallel accumulator module (Parallel Addersubtractor 2) is used as an initial frequency offset accumulator to provide an offset to the input frequency control word so that the output frequency starts to change from an initial frequency that can be defined by the user.

The bus width conversion module (Bus Conversion) is used to extract only the upper 10 bits of the bus signal and use them as the address driving signal for the data lookup table module. In order to facilitate the next step of design, Figure 5 is encapsulated into a subsystem module (Subsystem Block) and named: DDS_Subsystem, as shown in Figure 6.

In FIG6 , in1 is the initial phase input terminal, in2 is the input frequency control word terminal, and in3 is the initial frequency input terminal.

3 Design of frequency conversion control module

According to the properties of the Chirp function in the frequency domain, it can be concluded that there are two types of corresponding relationships between the input control word and the output frequency: linear and nonlinear:

First, the single-step increase/decrement submodule (Increment/Decrement Block) in the DSP Builder library is used to establish a sampling point control word generation unit. This module can generate control word signals one by one in a step-by-step manner and maintain a period of time set in the module setting item (Clock Phase Se-lection). When the increase or decrease direction (Direction) is set to Increment, the time domain output is obtained, as shown in Figure 7.

Secondly, a control word conversion module is established as needed, that is, the sampling point control word output by the Increment/Decrement module is converted into the frequency control word of the DDS. This needs to be based on the change rules of different Chirp functions. For example: if the output is a linear frequency, the sampling point should have a linear function correspondence with the output frequency; if the output is a nonlinear frequency, the sampling point should have a nonlinear function correspondence with the output frequency. This submodule is established according to different transfer functions:

For example: fout=kn+f0. When k=3, the submodule is established as shown in Figure 8.

After the above modules are generated into sub-modules, the overall simulation of the connection is shown in Figure 9.

And establish FFT observation window at the output end of DDS.

4 Verification and Simulation

Assume that the initial phase is 0, the initial frequency is also 0, and the sampling point step control word is set to output 12 for the step cycle increase mode. The graph observed in the time domain output observation window (Scope) is shown in Figure 10.

As can be seen from Figure 11, the frequency of the output signal changes periodically and regularly, proving that the design can well implement the function of the Chirp signal source. And through the SignalComplier tool provided by Altera DSP Builder, it is easy to generate HDL (VHDL or Verilog HDL) code and download it to the FPGA for execution, greatly simplifying the FPGA design.

5 Conclusion

According to the specific input/output (linear and nonlinear) relationship of the Chirp function, the corresponding relationship between the current input word and the output frequency is calculated, and then the control word submodule is designed to generate the frequency control word of the DDS module to drive the DDS to generate different output frequencies. Through simulation verification in the Simu-link environment of Matlab, the spectrum diagram of the output at different times is obtained, which verifies that the design can well realize the Chirp signal source.