Application of ADSP2189M in the development of automatic ship identification system

　　Introduction
　　The AIS system is a collision avoidance system that uses TDMA technology to exchange data in the maritime mobile VHF band. It is one of the equipment that every ship must be installed by the International Maritime Organization. Product development is based on the ITU-R M1371 protocol promulgated by the International Maritime Organization. ADSP2189M is used as its data processing platform during development to complete various data processing, conversion, time slot division, network login and maintenance and other algorithms to realize most of its main functions. The system model is shown in Figure 1.

　　The radio station receives the GMSK signal at the two frequencies of 161.975MHz and 162.025MHz. The GMSK modulation and demodulation chip converts the analog data into a digital signal. The data stream passes through the host computer to complete the determination of the correct data and delete the data segment. The start, fill and end bits are sent to the DSP through the parallel port. The DSP completes the processing and analysis of the received data, establishes the time slot table of the entire sea area, completes the network login and maintenance of TDMA, and then sends the relevant data to Different formats are sent to different serial port outputs. According to the ITU-R M.1371 protocol, they are connected to the network in ITDMA (Incremental Time Division Multiple Access) mode and run continuously in SOTDMA (Autonomous Time Division Multiple Access) mode to achieve TDMA of the entire network. Integrity. Therefore, the signal processing unit plays an important role in the system.

Figure 1 DSP and external device interface

ADSP2189M chip
　　The ADSP2189M chip is a fixed-point DSP with an instruction cycle of 13.3ns and an operating speed of up to 75MIPS. The processor includes an arithmetic/logic unit (ALU), a multiplier/accumulator (MAC), and a barrel shifter. The memory adopts Harvard structure, with 48K PRAM and 32K DRAM. Two SPORT synchronous serial ports, a timer and the host interface can be directly connected to the host processor. The DMA interface includes the internal DMA interface (IDMA) and the byte DMA interface (BDMA).

The hardware design of 2189M in the AIS system.
　Part of the circuit is shown in Figure 2.
·The chip is connected to an external 33M crystal, and its internal frequency is automatically multiplied to 66M;
·A synchronous serial port SPORT is connected to the external MCU, and the pin must be connected to a pull-up resistor;
·Set SPORT1 to the second working mode, and use software to switch the I/O The O port simulates UART, connects to the MAX232 chip, and the data is sent to the simple display;
·Use IDMA mode to connect to the MCU, 16 parallel port lines are connected, the startup mode is set to IDMA mode, and its 4 MODEA~D settings are 1, 0, 1, 0;
·The steps to complete IDMA boot loading are as follows;
The four debugging pins PWD, EBR, BR, and ERSET must be connected to external pull-up resistors;
finally write the value of PM (0X0000), and the program will start to execute automatically.

Figure 2 Partial circuit diagram of the AIS system

Figure 3 Serial port receiving timing diagram

Figure 4 Time slot division diagram

The software design of the ADSP2189M interface and
the setting of Sport0
use the synchronous serial port to communicate with the MCU

　　DM (0X3FF6) - the serial port control register settings are shown in Table 1.

　　In Table 1, 0~3: receive and send word length, which we define as 16-bit word length, set to 1111. 6~7: frame synchronization signal level, 0, high level is valid. 8~9: Frame synchronization signal source, which is 1, and the frame synchronization signal is generated internally.

　　10~11: Framing mode, 1, second framing mode. 12~13: Frame synchronization, which is 0. A frame synchronization signal is required to initiate communication. The frame synchronization signal will no longer be considered in the future. 14: SCLK generation mode, which is 1 and the serial clock is generated internally.

　　DM(0X3FF5)—Serial port clock frequency division coefficient register dm(sclkdiv)
　　In the ADSP2189 chip, the relationship between the sampling rate and the frequency division number is as follows: F(sclk)=f(clkout)/(sclkdiv+1)/2

　　where , F(sclk) represents the running clock, F(clkout) represents the output clock of the external crystal oscillator, sclkdiv represents the frequency division number, that is, the value that the memory should be assigned.

　　After the control register is set, the serial port receiving timing is shown in Figure 3. The received data is placed in the receiving buffer area. After each set of data is received, the receiving flag bit is written once. The main program detects the flag bit regularly. When the flag is detected When the bit changes, the reception processing subroutine is called.

Settings of Sport1 and timer:
　　Since the DSP needs to output data to a simple display and connect through the UART port, Sport1 is set to the second working mode (as shown in Table 2).

　　DM(0X3FFF)—system control register (as shown in Table 3).

　　In Table 3, 12: SPORT0 enablement, set to 1. 11: SPORT1 enablement, set to 1. 10: SPOER1 function selection, set to 0.

　　Use the I/O port to simulate UART and sample at a baud rate of 9600. The internal timer interrupt generation rate is 3×9600. Three samples are generated during a level transition, and the middle sample value is valid.

DM (0X3FFD)—timing period register
DM (0X3FFC)—timing counting register
is connected to an external 33M crystal. The value stored in the register is:
period=frequence×2/(3×9600)-1=2314

　　The chip generates an interrupt at a baud rate of 28800. Each interrupt program detects the UART flag bit. When the flag bit changes, the I/O output is set every 3 interrupts until the end of sending data.
Part of the code settings are as follows:
ax0 = 2314; //Timer setting
dm(0x3ffc) = ax0;
dm(0x3ffd) = ax0;
ax0 = 0;
dm(0x3ffb) = ax0; //Control register setting
ax0 = b#0001100000000000 ;
ax0=b#0111111000001111;
dm(0x3ff6)=ax0; //sport0 setting
ax0=0x001f;
dm(0x3ff5)=ax0; //SCLKDIV0
mstat = 0x10; //Multiplier setting
ifc=b#0000000001100001; imask=b #0000100001; //Interrupt and enable
ena timer;
//Enable timing

The main software process
　　system adopts autonomous time division multiplexing, dividing time into periodic frames, and each frame is divided into a number of time slots (no matter the frames or time slots are non-overlapping), each time slot is a communication channel , assigned to a user. According to certain time slot allocation principles, the system allows each mobile station to transmit signals (burst signals) to each other only in designated time slots in each frame. Under the conditions of meeting timing and synchronization, the base station can transmit signals to each other in each time slot. Signals from each mobile station are received without interfering with each other.

　　Divide the space of the two channels in the register as the time slot table of the sea area, as shown in Figure 4.

　　Network login uses a probabilistic persistence algorithm (when a candidate time period is found, the station randomly selects a probability value LME.RTP1 between 0 and 100, and compares this value with a probability LME.RTP2 between 0 and 10. If LME.RTP1 If it is less than or equal to LME.RTP2, this time period is selected. Otherwise, LME.RTP2 plus a probability increment is compared with the next candidate time period). Randomly select an idle time slot as the access point of the network in 2250 time periods, and then access it in ITDMA mode. This method is a form of reporting first and occupying first. In the currently transmitted data, the next time slot number that needs to be sent is specified, so as to notify other stations in advance of the time slot number occupied by itself, which is determined within 60 seconds. The space required. In the subsequent continuous stages, the mobile station completes network maintenance and time slot re-division in SOTDMA mode. Since the data format stipulated in the protocol can only predict the occupancy situation for a maximum of 7 minutes, so every 7 minutes, a new idle time slot needs to be selected within a certain range for transmission, and so on, in this continuous state. Keep running.

　　When the speed changes, the system re-uses ITDMA to complete network login at the new speed.

Conclusion:
　　The design scheme proposed in this article makes full use of the high-performance data processing function of DSP and the real-time and stable characteristics of the embedded operating system, and uses a time-division multiplexing algorithm to perform network division and connection functions within a sea area. This model of combining DSP signal processing with embedded operating systems can be widely used in the field of communications and has broad application prospects.

References
1 Wu Minyuan. Principles of ADSP series digital signal processors. Electronic Industry Press
2 Su Tao. Wu Shunjun. Liao Xiaoqun. High-performance digital signal processors and high-speed real-time signal processing. Xi'an University of Electronic Science and Technology Press