Programmable DSP architecture for TD-SCDMA and TD-LTE designs

Programmable DSP architecture for TD-SCDMA and TD-LTE designs

As the world's largest mobile market, China hopes to develop mobile standards that are different from those of Europe and the United States. That is, the current 3G standard TD-SCDMA and the future 4G standard TD-LTE.

In early 2006, the Chinese government announced that TD-SCDMA would officially become China's 3G mobile communication standard. In 2009, China Mobile, the world's largest mobile operator, announced that it would provide 3G services based on the TD-SCDMA standard. At the same time, China Unicom and China Telecom will launch 3G services based on the WCDMA and CDMA-2000 standards respectively. This means that China will have three different 3G networks in the future.

It is obvious that the launch of 3G services in China is much later than that of Europe and the United States. China Mobile realized that it could not rely solely on TD-SCDMA to ensure its current leading position. Therefore, China Mobile has set its sights on the future 4G standard LTE while launching TD-SCDMA. Therefore, China Mobile may also skip 3G and evolve to LTE as soon as possible.

Based on the current situation, it is difficult to accurately predict which standard will dominate the Chinese mobile market in the future. Therefore, as a terminal baseband chip supplier, it is currently facing a very difficult choice. If you only develop for a certain standard, you may bet on the wrong standard. If you design a baseband that supports multiple standards, the traditional baseband design method based on hardware accelerators will greatly increase the difficulty, cost, risk and lack of flexibility. In this case, engineers will naturally look for programmable solutions, which can provide sufficient flexibility and shorten the development time for multiple standards.

Different ways to design wireless basebands

There are usually three ways to design wireless basebands:

• Traditional hardware method - the baseband is implemented entirely in hardware. This method basically allows the first chip to be launched on the market quickly. At the same time, this design can ensure the lowest power consumption. However, the chip designed based on this method has no flexibility and is difficult to upgrade to support subsequent products.

• Software radio method - a completely soft baseband method is implemented, and the same chip can support multiple different standards at the same time in software. This method only needs to switch software to support different standards, without changing the chip design at all. However, the main problem with this method is the complexity of the programmable engine design and the higher power consumption compared to the hardware method.

• Hybrid method - DSP plus hardware accelerator. In this way, the processing part of the baseband that requires flexibility can be implemented on the DSP in software, and the remaining computationally intensive and relatively fixed processing parts, such as FFT, can be implemented in hardware accelerators.

Considering the high risk of pure hardware design, this article will focus on two other programmable baseband design methods.


Figure 1 CEVA-XC block diagram

Figure 2 CEVA-X1641 block diagram

Software radio design based on CEVA-XC

CEVA-XC is a high-performance communication processor optimized for the most advanced wireless standards (block diagram shown in Figure 1). CEVA-XC, built on the CEVA-X system, can fully support multiple advanced wireless standards in software, including the most complex 4G standard LTE Cat.5 and WiMAX II (IEEE 802.16m), as well as 3G and 3.5G. This innovative processor can run multiple different wireless standards simultaneously in a pure soft baseband mode.

A CEVA-XC can support multiple different wireless standards simultaneously in software, so there is no need for hardware accelerators designed for different standards. Therefore, the power consumption and area of ​​the entire system can be reduced.

The CEVA-XC architecture can contain 1, 2 or 4 vector processors. Each vector processor is a 3-issue, single instruction multiple data (SIMD) engine that can process 256-bit wide data. It includes 16 MAC units, arithmetic, logic and shift units. The instruction set of CEVA-XC can handle the processing requirements of 4G baseband, such as matrix processing, MIMO detectors, complex filtering, data permutations and bit processing.

Hybrid Baseband Design Based on CEVA-X1641

CEVA-X represents a series of general-purpose high-performance DSP processors that are widely used in wireless baseband applications and have been mass-produced in products of multiple baseband chip vendors. CEVA-X

is an architecture based on Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD). VLIW allows multiple instructions to be executed simultaneously to ensure a high degree of instruction-level parallelism while ensuring low power consumption. The CEVA-X architecture has good support for C language, which can help developers greatly reduce development costs and shorten time to market.

CEVA-X1641 is a member of the CEVA-X family (block diagram shown in Figure 2). It has four 16-bit wide MACs. CEVA-X1641 can reach a worst-case operating frequency of 700MHz in a 65nm process.

As a high-performance and easy-to-program DSP, CEVA-X1641 allows designers to flexibly partition their terminal baseband SOC designs into software and hardware. Different baseband customers use different software and hardware partitioning methods and single or multiple DSP cores in their designs. In addition, it can also guarantee customers' software investment and software reuse in future evolution products. Currently, multiple CEVA customers are using CEVA-X1641 to design their 4G wireless basebands.

Conclusion

It is precisely because of the reality of the coexistence of multiple standards in the future Chinese wireless market that it is necessary to use the same platform to support multiple different standards. Both the pure soft baseband method based on software radio and the hybrid programmable method can provide sufficient flexibility to meet the needs of reuse and rapid market launch.

For a long time, the leaders of the wireless baseband market have made it clear that programmability is the direction of wireless baseband development. The two CEVA DSP cores discussed in this article provide suitable solutions based on the different needs of authorized customers for chip architecture and flexibility.