Introduction to the Principle of DSPLL

Principle of DSPLL

This technology uses DPS high-speed computing to replace the phase-locked loop filter circuit that is usually built with discrete components. Since no external components are required, the impact of board noise on the phase-locked loop is minimized. This digital technology can provide high stability and consistency under temperature, voltage changes and different peripheral MCUs. The figure below is a simple functional block diagram of DSPLL.

DSP operation processes the phase difference pulse of Phase Detector and generates a digital frequency control word M to modulate a digitally controlled clock DCO. Digital dividers N1, N2, and N3 all have a large range, so that an output of approximately any frequency can be generated under an input frequency. Narrow loop bandwidth products with DSPLL technology (Si5316, Si5319, Si5323, Si5326, Si5366, and Si5368) provide ultra-low output jitter and extremely strong jitter attenuation performance. For applications that require multi-channel low-jitter clock frequency conversion, wide loop bandwidth products (Si5322, Si5325, Si5365, and Si5367) are a good choice.

Advantages of DSPLL

(1) Extremely low output jitter 0.3ps RMS jitter.

(2) Wide range of input frequency and output frequency.

Input frequency: 2KHz-710MHz

Output frequency: 2KHz-1.4GHz

Since digital dividers have a large range, they can guarantee a wide range of input and output frequencies. When building a complex clock system, especially as a clock platform, it can be used in various occasions by simply changing the software and pin configuration, while competitors' chips require changing the chip model and redesigning.

(3) Adjustable loop bandwidth: 60Hz-8.4KHz. Using DSP technology to make the PLL low-pass filter brings a very big advantage that the loop bandwidth can be adjusted by changing the register, which is suitable for a variety of signal quality environments.

(4) Extremely low phase noise index. The use of internal integrated filters in the chip can effectively reduce the noise interference from the single board.

(5) High integration, simplified phase-locked loop design and layout

Traditional phase-locked loop chips require customers to design low-pass filters by themselves, and take EMC protection measures for low-pass filters. Special attention is also required when laying out the board. Since Silicon Labs PLL has basically no peripheral devices, there is only one clock input as a reference. The chip design is configured by DSPLLsim software, and there is no mandatory requirement for board layout.