CPLD with automatic power off

Today, most CPLDs (Complex Programmable Logic Devices) operate in modes that reduce power consumption, but when the system is not in use, power should be completely cut off to conserve battery energy, thus achieving the ultimate energy saving goal of many designers. Figure 1 describes how to add several discrete components to a CPLD to implement a system power-down circuit that saves battery energy. In this example, the CPLD used is an Altera EPM570-T100. An external P-channel MOSFET Q ₁ and an International Rectifier ( www.irf.com ) IRLML6302 (or equivalent) are used to form a power control switch for IC _{1 CPLD.} The CPLD and switch matrix control the gates of the MOSFETs, and when the user presses a switch, the switch's bias voltage is applied across _Q1 . The CPLD has an embedded timer for monitoring switch and system operation. When the system is in a specific inactive period, the timer will remove the gate drive of the MOSFET, causing the CPLD and other components connected to the MOSFET to power down.

The source of 　　Q ₁ is connected to the positive terminal of the battery, and its drain is connected to the V _{CC (INT)} , V _{CC (IO1)} and V _{CC (IO2) power pins of IC 1} and other components that require power-off control. When the power supply is disconnected, a 1kΩ pull-up resistor R ₃ maintains the gate-source voltage of Q ₁ at 0V, maintaining its off-state. When IC ₁ is powered off, it establishes a leakage path to ground through the CPLD's power-down pin. EPM570T100 is equipped with hot plug protection, which can limit the current of any user-accessible device's I/O pin to less than 300mA. Therefore, even in the worst case scenario, the I/O pin voltage developed across R ₃ will not reach the FET's minimum gate threshold turn-on voltage of 0.7V. 　　Pressing any switch establishes a current path through the switch's contacts and the corresponding diode, thus creating a gate-source bias voltage of about 2.3V on _{R3 . This voltage is enough to turn Q1} on for about 100ms and provide IC ₁ supplies power. When mechanical switches are activated, their minimum on-time is at least 3ms, and a typical operator's press/release time is at least 30ms. Since the human response time is relatively slow, before the operator releases the switch, the CPLD can complete the conduction, reset the internal circuit, and maintain the power-off pin of Q _{1 in a logic zero state.} 　　In addition to the application logic set by the user (not shown in the figure), the power control logic of the CPLD adds a pair of library macro circuits with standard parameters, which are generated by the Quartus II development tool of Altera ( www.altera.com ). The internal 4.4MHz ±25% oscillator Altufm_osc drives a modular 44 million LPM (library parameterized module) counter. The counter is reset by a logic low signal generated by the CPLD application logic or by closing any switch. When the counter is reset, its execution signal goes low, driving the external power-down pin. When reset is removed, the inverted execution signal restarts the LPM counter. 　　If all switches are on and the application logic is not working, the counter counts to 44 million in about 10 seconds, and then the internal execution signal goes high, turns off the counter, and keeps the execution signal high. Next, the power-down pin climbs toward V _CC , and when the power-down pin voltage reaches 2.3V, Q ₁ is turned off . Turning off power to the CPLD causes the power-down pin to enter tri-state (or unconnected) mode, and R ₃ keeps Q ₁ off. 　　Users can configure the EPM570-T100 using JTAG-compliant commands and connecting a download cable to a factory-defined 10-pin plug. This process requires pressing an external switch before, during, and after configuration to ensure that the CPLD can obtain power during the configuration process. The inactive time can be set to any desired value by changing the counter module. Although dedicated device pins are used for power, ground, and JTAG signals, any general-purpose CPLD I/O pin can be programmed as a switch input and power-down output. 　　If your application requires a key switch matrix, you can use n diodes to form an nxm switch for effective power-on detection (Figure 2). In this example, rows of switches are connected to the gates of the MOSFETs through diodes D ₁ to D _{4 .} Resistors R ₈ ~ R ₁₁ provide a path to ground for each row switch and only carry current when the switch is closed, making the row input low while ensuring that only minimal power supply current is consumed.

　　When the user presses either switch, the gate of Q ₁ is low and the CPLD is turned on. Before the user releases the switch, a quick CPLD power-up routine scans the rows and rows of the switch array to determine which switch the user pressed. And the reset signal resets the inactive timer of the LPM counter.