Gigabit Ethernet Communication Based on FPGA-on-chip PowerPC in VxWorks

At present, SoC is developing towards a smaller area and higher speed. 100M network communication can no longer meet people's production and work needs. Gigabit network communication has become an urgent requirement in work. There are two modes to choose from to achieve Gigabit network communication with FPGA. One is to write an IP soft core, and the other is to use the MAC core embedded in FPGA. Method 1 is flexible, but it is not easy to implement. Therefore, Xilinx classifies it as a paid IP; the three-state configurable characteristics of MAC in method 2 make it possible for us to achieve Gigabit network communication. This article is based on this embedded Ethernet MAC module and successfully implements Gigabit network communication under the VxWorks operating system.

1 Gigabit communication hardcore architecture embedded in Virtex4 FX series FPGA

Virtex4 FX series FPGAs have multiple hard cores embedded for Gigabit communication. For example, XC4VFX20 connects two EMAC cores through a host interface. The two EMACs can be used together or only one of them can be used.

The Ethernet MAC hard core embedded in Virtex4 has the following features:

Supports half-duplex and/or full-duplex operation

Designed to comply with IEEE 802.3-2002 standards

Supports 3 different operation modes: 1 Gbps, 100 Mbps, 10Mbp

Support MII, GMII, RGMII, SGMII communication methods

Provide technical support for VLAN frames and JUMBO frames of unlimited length

Provides optional network management features including per-packet statistics vectoring and flow control

The TEMAC core can be configured and monitored through a processor-independent interface, providing users with additional flexibility in selecting the ideal processor for their application.

In 1Gigabit mode, TEMAC supports Gigabit Media Independent Interface (GMII) and Reduced Gigabit Media Independent Interface (RGMII). GMII is a byte-wide parallel SDR interface running at 125 MHz, while RGMII is a half-byte parallel DDR interface running at 25 MHz, providing a total bandwidth of 1 Gbps. In addition, TEMAC supports MII interface in both 100 and 10 Mbps modes. MII interface is 4-bit wide and operates at 25 MHz in 100MBps mode. In 10MBps mode, MII interface operates at 2.5MHz.

Since the Ethernet MAC hard core is embedded in Virtex4 and PowerPC is also embedded in the FX series, PowerPC can be used to control Ethernet MAC to achieve Gigabit network communication.

2 BSP Porting under VxWorks

The VxWorks operating system is an embedded real-time operating system (RTOS) designed and developed by the American WindRiver Company in 1983. It adopts a microkernel structure, supports multiple processors, has rich network protocols, good compatibility and scalability, and has the function of dynamic linking and downloading programs. Since its launch in the 1980s, it has gradually occupied a place in the field of embedded real-time operating systems with its continuously launched upgraded versions, high-performance kernel and user-friendly development environment, and has become famous for its successful application in high-tech products such as Mars Exploration Rovers and Patriot Missiles. The board support package BSP (Board Support Package) of VxWorks is a low-level software development package between the underlying hardware and the upper-level software. Its main function is to shield the hardware and provide the operating system driver. The specific functions include:

1) Single board hardware initialization, mainly CPU initialization, provides underlying hardware support for the entire software system;

2) Provide device drivers and system interrupt service routines for the operating system;

3) Customize the operating system functions to provide a real-time multi-tasking operating environment for the software system;

4) Initialize the operating system and prepare for the normal operation of the operating system. [page]

In embedded system design, BSP development is a very complex and tedious task. The EDK suite provided by Xilinx can greatly reduce the work of developers. The BSP generator (BSPgen) in EDK can automatically generate user-customizable BSPs based on different microprocessors, peripherals, and RTOS combinations. It contains the necessary support software for the system, including Boot code, device drivers, and RTOS initialization. BSPgen can be used to package Xilinx device drivers into a subdirectory of the BSP, and seamlessly integrate Xilinx device drivers with VxWorks and its Tornado integrated development environment, fully reducing the development cycle.

However, the BSP generated by BSPgen is only a fixed BSP template, which cannot correctly reflect the memory mapping of RAM/ROM and does not support the kernel/driver customized by the user through the BSPgen process. Therefore, the BSP generated by BSPgen needs to be modified and tailored.

For BSP developers, with the help of EDK's BSPgen, it is also necessary to do the following tasks:

1) Modify the RAM, ROM address and serial port rate in config.h and Makefile

2) Modify sysSerial.c and set the serial port correctly

3) Add driver files for devices that cannot be seamlessly integrated with VxWorks

4) Configure Ethernet parameters in sysNet.c and set the MAC address

5) Disable or enable Cache according to the configuration in EDK

6) Modify sysLib.c to display the correct information

7) Set the host IP address

After the above modifications, place the new BSP in the Tornado installation directory Tornado_roottargetconfig. Based on this BSP, generate a new VxWorks project in the Tornado integrated environment, and then you can carry out general embedded operating system development.

The address mapping of RAM and ROM in EDK is shown in the following table:

Table 1 RAM/ROM address mapping

Modify the addresses in makefile and config.h according to Table 1. The MAC address of the network is defined in sysNet.c by the following statement, which must be modified according to the actual MAC address, such as the MAC address in this article: 00:0A:35:01:88:25

static char XEmacMacAddr0[6] = { 0x6, 0x5, 0x4, 0x3, 0x2, 0x1 }; //Before modification

static char XEmacMacAddr0[6] = { 0x00, 0x0A, 0x35, 0x01, 0x88, 0x25 }; //After modification

sysSerial.c initializes the serial port. Since the serial port ID must be correctly specified, sysLib.c can display the information of the vxWorks image, so corresponding modifications must also be made.

After modifying the BSP generated under EDK and generating the correct VxWorks image in the Tornado integrated environment, it can be downloaded to the FPGA. Observe whether the serial port output is correct and perform corresponding debugging to confirm that the BSP transplantation is correct.