FPGA Implementation of High-Speed ​​Burst Mode Bit Error Tester

introduction

Passive optical network PON has been applied on a large scale in the network with its unique advantages. Since the GPON system has the highest bandwidth utilization rate, the lowest system cost and the ability to support all services among the existing PON systems, its prospects are generally optimistic and it has become a broadband access technology highly praised by many telecom operators and equipment manufacturers.

In GPON, downstream data is sent in broadcast form, and upstream data consists of data packets sent by multiple user terminals in a time-division multiple access manner. Due to different transmission paths, each data packet has different attenuation, there are jumps between the phases of different data packets, and there are long continuous "1" and "0" in the data packet. The influence of these factors makes the signal received by the OLT burst receiving module a special burst optical signal. For the upstream burst signal, the OLT burst receiving module must not only recover the signal with equal amplitude, but also eliminate the phase mutation, that is, complete the alignment of the clock and phase. Therefore, the signal output by the OLT should be an electrical signal with equal amplitude and aligned clock and phase. The function of this burst mode bit error tester is to accurately determine the amplitude recovery response time and reliability of the OLT burst receiving module under test.

1 Principle of Burst Mode Error Test

Similar to the general continuous bit error tester, the burst bit error tester also consists of two parts: the sending part and the receiving part. The sending part sends a predictable signal as a test signal to simulate the transmission signal in the actual channel, and sends the signal to the device under test; the receiving part generates the same signal as the sending part, which is used to compare the received signal bit by bit and count the number of bit errors and the bit error rate.

Different from the general continuous bit error tester, the test signal sent by the burst bit error tester must simulate the burst signal, that is, it has the characteristics of phase jump and amplitude imbalance. In addition, the receiving part must accurately extract the clock and recover the data from the received signal that may have phase jump.

According to the characteristics of the burst error tester, its overall design block diagram is shown in Figure 1.

The burst receiver module (BMRx) is the module to be tested. The burst error tester uses FPGA logic to implement the output of two-way time division multiplexing (TDMA) data. The two-way data first passes through the optical variable attenuator with different attenuation amplitudes, then passes through the delay of different lengths of optical fiber, and finally passes through the optical combiner to combine into one signal output. The output data of the optical combiner is close to the actual upstream burst signal in GPON, and it is assumed that there is no error in the signal after passing through these paths. After the simulated burst signal passes through the burst receiver module to be tested, it extracts one packet data (ON-U#1 or ONU#2) through the packet separation circuit. The packet data finally passes through the burst mode clock data recovery chip to extract the clock and 4 parallel data. The FPGA uses the extracted clock as the source clock for error comparison, and reconstructs the 4 parallel data and compares it with the locally generated data to count the error. [page]

2 Design of logical function modules in FPGA

As an important chip for implementing burst mode bit error tester, FPGA mainly realizes the following functions:

① The transmitter generates two high-speed time-division multiplexing signals. These two signals must have the characteristics of GPON upstream data packets, namely 32-bit protection time, 44-bit preamble, and 20-bit delimiter.

② The receiving part converts the received 4-bit wide data into 8-bit wide data, and searches for the delimiter to align the boundaries of the received data.

③ The error detector compares the received boundary-aligned data with the locally generated pseudo-random code and only counts the errors that occur in the valid data.

④Synchronization detection and resynchronization after loss of step.

Figure 2 shows the main logic function modules implemented in FPGA.

① The control signal decoder assigns the control information to the corresponding control signal of the error test logic module according to the address information input by the Microblaze microprocessor through GPIO_IN. The control information mainly includes: packet length, protection time length, preamble length, code type selection, DRP address and value of GTP attributes, control information of the clock synthesis chip, etc.

②The status encoder stores the status information of the error test module and maps it to GPIO_OUT at different addresses, and then transmits it to the Microblaze microprocessor. The output status information mainly includes: number of error bits, total number of received codes, synchronization status, no signal received, etc.

③ The pattern generator module includes two sub-modules: the PRBS generator and the data packet header generator. The PRBS generator generates an 8-bit width pseudo-random sequence of the corresponding pattern according to the pattern selection control signal, and the data packet header generator simulates the characteristics of the GPON upstream data packet header structure to generate patterns similar to the preamble and delimiter. The pattern generator module also includes a data packet encapsulation finite state machine, whose main function is to generate a control signal for the transmission code state, and to intersperse the header data, packet interval (protection time), and CID (long connection O/1) in the PRBS to simulate the GPON upstream data. The data txdata containing two packet signals is separated into two time-division multiplexed signals txdata0 and txdata1 after being ANDed with the packet separation signal. The timing is shown in Figure 3.

④GTP0 and GTP1 are the cores of the FPGA chip. It converts the low-speed 8-bit parallel data txdata1 and txdata2 into a high-speed serial data. The data transmission rate can be changed by modifying the DRP attribute of GTP. GTP is also responsible for providing a synchronous clock to the transmitter.

⑤ The data reconstruction module converts the received 4-bit wide data into 8-bit wide data, and searches for the 16-bit delimiter to align the boundaries of the received data.

⑥ The error detector is mainly composed of a local pseudo-random sequence generator, a receiving state machine and a synchronization detection state machine. The local pseudo-random sequence generator has the same order and primitive polynomial as the random sequence generator at the transmitting end. The pseudo-random data it generates is compared with the received data, and the comparison result is counted by the error counter. The receiving state machine determines whether the received data is valid data based on the delimiter detection signal and the packet length (packet 1 or packet 2) counter, and generates a valid data indication signal. The synchronization detection state machine determines whether the data generated by the local random sequence generator is synchronized with the received data based on the comparison result. If not, the local pseudo-random sequence generator will intercept a 32-bit continuous signal from the received data as the initial value of its shift register to generate the subsequent data for resynchronization (code injection synchronization).

⑦ The bit error counter is used to count the number of bit errors. It only counts the bit errors that occur in valid data. The receive word counter is used to count the number of valid data bytes received. [page]

3 Control system design

In this design, Microblaze embedded soft-core processor is used to realize the control of the logic part of the bit error tester. The hardware block diagram of the control part is shown in Figure 4. GPIO1 is used for communication between the processor and the BERT core; GPIO2 is connected to the LED and the dip switch to display the status and control the bit error tester at the board level; GP103 is connected to the LCD to display the bit error test results on the LCD; counter-er 64 is a 64-bit wide counter for timekeeping. UART is connected to the computer through RS232 to read the control information set on the PC and display the bit error test results and the status of the bit error tester in detail on the PC.

The functions included in the control program mainly include GPIO driver, UART driver, LCD driver, GTP DRP attribute read and write function, BERT control and status reading function, bit error rate calculation function, main function, etc. The main function provides a platform for users to interact with the bit error tester, and its process is shown in Figure 5.

After power-on or reset, the system initializes LCD and UART, and loads the last saved user settings to initialize BERT. Then enter the main menu, where you can enter the corresponding operation by selecting the corresponding option. By reading the last saved user settings loaded by the error test, check whether the settings required by the user this time are the same as the settings saved last time. If they are different, you can return to the main menu and enter the corresponding setting operation from the main menu to modify the parameters. After the modification is completed, if the user wants to save the settings, he can save them and then return to the main interface; if you do not need to save, return to the main interface directly. From the main interface, you can select the error test display to enter the error test result display interface. Before displaying the error test results, the control program will first calculate the error rate to ensure real-time display of the error test results.

4 System Verification and Design Summary

In order to verify the performance of the system, the instrument was used to perform self-loop test and error test on the burst optical receiving module of the 1.25 GHz GPON system. In the self-loop test, the transmitted data is directly sent to the receiving end of the BMCDR without passing through the optical path. The test results show that the error test system itself will not have error in the electrical signal channel. In the test process of the burst optical receiving module of the 1.25 GHz GPON system, a two-step test is adopted. In step 1, the error test system is connected according to Figure 1. The two data packet signals 0UN#1 and 0UN#2 are not attenuated by the variable optical attenuator. The amplitudes of all packet signals in the optical signal after being combined by the optical combiner are consistent, which is used to verify whether there is error in the optical path of the error test system. The experimental results also verify that the error test system itself will not have error. In step 2, one data packet signal is attenuated with different amplitudes, so that the optical signal output by the optical combiner has an amplitude jump, and the error performance of the burst optical receiving module is tested separately when the two data packet signals have different amplitude jumps. The amplitude difference between the strong and weak packets of the burst optical receiving module used in the test is 20 dB, the protection time is 32 bits, and the bit error rate is lower than 10-12 when the rate is 1.248 8 Gbps. This shows that this bit error test system has good performance.