Application of CPLD in the power supply of ozone generator

Publisher:行者无疆1978Latest update time:2010-08-11 Source: 电子设计工程Keywords:CPLD Reading articles on mobile phones Scan QR code
Read articles on your mobile phone anytime, anywhere

Ozone is known as a "green" disinfection product and is widely used at home and abroad. In recent years, ozone technology, as an important part of the environmental protection industry, has attracted more and more attention. Related products have expanded from drinking water treatment systems to sewage treatment, air purification, household environmental pollution prevention and control, medical care and other fields.

The power supply of the ozone generator is an important part of the ozone generator. The voltage, frequency and waveform of the power supply are important factors affecting the efficiency of the ozone generator. After the structure, gas source and cooling system of the generator are determined, the performance and quality of the power supply system become the key to affecting the efficiency of the generator. After the 1980s, the development of semiconductor devices has brought about a qualitative change in the ozone power supply, and the inverter power supply has become the main form of ozone generating power supply. In this type of power supply, the industrial frequency AC power is rectified into DC power by a rectifier, converted into single-phase medium and high frequency AC power by an inverter circuit, and then boosted to the voltage required for the generator to discharge by a medium and high frequency step-up transformer. Compared with the industrial frequency power supply, the medium frequency inverter power supply has the advantages of small system size, high power efficiency, large ozone output, wide linear adjustment range, and low pollution to the power grid.

1 System Hardware Design

In the design of the ozone generator power supply, the commutation voltage drop generated by the thyristor SCR during three-phase rectification will have a serious impact on the output voltage average value and voltage waveform. Therefore, in the design of the main circuit of the power supply, high-power diode rectification is used to replace SCR rectification, so that the voltage pulsation output by the rectification circuit is very small, thereby improving the stability and efficiency of the power supply.

Since the rectifier part of the power supply uses uncontrollable diodes for rectification, the output voltage cannot be adjusted through the rectifier part. Therefore, the output voltage and frequency of the power supply can only be adjusted through the inverter part, that is, by controlling the duty cycle and frequency of the inverter trigger pulse, the output voltage and frequency of the power supply can be adjusted to meet the design requirements. The following focuses on how to adjust the duty cycle, frequency and soft start time.

[page]

1.1 Duty cycle adjustment unit

Figure 1 is a duty cycle adjustment circuit. This circuit uses the voltage signal output by the regulator as the input signal of the voltage controlled oscillator VCO (Voltage Controlled Oscillator). This signal is a DC voltage signal that varies between 0 and 5 V, namely the INPUT signal. Since the VCO is a current controlled oscillator, the charging current of the timing capacitor C1 is proportional to the control voltage input from pin 9, so that the oscillation frequency of the VCO is proportional to the control voltage. When the VCO control voltage is 0 V, its output frequency is the lowest; when the input control voltage is equal to the power supply voltage VDD, the output frequency increases linearly to the highest output frequency. The range of the VCO oscillation frequency is determined by R1, R2 and C1. The VCO oscillation frequency is directly output from pin 4 of CD4046 to the CPLD processing unit. The CPLD controls the width of the inverter trigger pulse by counting the pulse signal to adjust the duty cycle of the trigger pulse.

1.2 Soft start time adjustment unit

Figure 2 is a soft start time adjustment circuit. This circuit unit uses the regulator output signal as the input signal of the voltage comparator LM339. This signal is a DC voltage signal (i.e., INPUT signal) that varies between 0 and 5 V. According to the design requirements, the given voltage of pin 6 of LM339 is 1 V. When the voltage of the INPUT signal is greater than 1 V, pin 1 of LM339 outputs a high level as a start signal to the CPLD through a pull-up resistor. The output of the comparator is controlled by adjusting the external dial switch inside the CPLD, thereby controlling the soft start time.

1.3 Frequency adjustment unit

Figure 3 is a frequency adjustment circuit. By adjusting the CD4046 external potentiometer POT11, the frequency of the VCO output pulse is controlled. According to the design requirements, the circuit will output a pulse signal PLS with a variation range of 1 to 6 kHz, and use this signal as the input signal of the CPLD. Through the counting delay and duty cycle design requirements inside the CPLD, an inverter trigger signal with a frequency between 400 and 3 000 Hz that meets the duty cycle requirements is finally output, and the frequency of the signal can be adjusted through POT11.

2 System Software Design

The system software design is designed according to the system functional requirements. The software program design based on EPM7128 is divided into: output pulse duty cycle adjustment, frequency adjustment, soft start time adjustment and overvoltage and overcurrent alarm. The development system uses VHDL language for modular programming, which can improve the portability of the program, shorten the development cycle, and reduce the development cost. It is also easy to maintain the system software and improve reliability. Figure 4 is the output of the two-way PWM pulse simulation waveform, where GCLK is a reference clock source, CLKl and CLK2 are the frequency adjustment and duty cycle adjustment signals converted by VCO, and SET and SOFT are two external 4-bit duty cycle adjustment and soft start adjustment switches.

3 Conclusion

The software and hardware design of the ozone power control system based on CPLD is introduced. The application of digital circuits in the power control system enhances the reliability of the system and makes the functions more complete. The control system can adjust the duty cycle of the output pulse and control the soft start time by adjusting the two external dial switches, making the power control more convenient and flexible. Through debugging on the industrial site, the control system can fully meet the control of the medium frequency ozone power supply, and has the advantages of strong anti-interference ability and good stability, and has a wide range of application prospects.

Keywords:CPLD Reference address:Application of CPLD in the power supply of ozone generator

Previous article:Design of hardware abstraction layer for FPGA based on SCA specification
Next article:Design of 16-bit high-precision digital voltmeter with CPLD as the control core

Recommended ReadingLatest update time:2024-11-16 16:44

Hardware Design of Digital Nuclear Pulse Analyzer Based on FPGA
Multi-channel pulse amplitude analyzers and ray spectrometers are commonly used instruments in nuclear monitoring and technical applications. In the 1990s, foreign countries had already introduced a new type of multi-channel spectrometer based on high-speed nuclear pulse waveform sampling and digital filter shaping te
[Power Management]
Hardware Design of Digital Nuclear Pulse Analyzer Based on FPGA
Multi-channel temperature acquisition system circuit and design based on CPLD
K-type thermocouple is a temperature sensor commonly used in current industrial production and scientific experiments. It can directly measure the temperature of liquid vapor, gas medium and solid surface in the range of 0 to 1,300°C in various production processes. Due to its measurement range and high cost perform
[Test Measurement]
Multi-channel temperature acquisition system circuit and design based on CPLD
How to build a circuit system using 51 microcontroller and CPLD chip
I. Introduction The single-chip microcomputer market can be described as a giant. Among them, the 51 single-chip microcomputer has more users. There is no need for more introduction to the 51 single-chip microcomputer. It must be emphasized here that as long as you are proficient in the 51 single-chip microcomputer, y
[Microcontroller]
How to build a circuit system using 51 microcontroller and CPLD chip
Using FPGA to implement low-cost virtual test system
      This paper uses FPGA to realize data processing and logic control, makes full use of PC, and combines the Labwindows graphical upper-layer application software interface to generate a virtual test system with strong competitiveness. Under the control of the FPGA single-board single-chip master device, this system
[Test Measurement]
Using FPGA to implement low-cost virtual test system
Design of Stereo LED Display Driver Based on FPGA
1 Introduction: LED video display screens have the advantages of high brightness, wide viewing angle, long life, low power consumption, high cost performance, and the ability to display various texts, graphics, and images synchronously with computers, play TV, video, DVD and other video signals in real time, an
[Power Management]
Design of Stereo LED Display Driver Based on FPGA
Design of high-precision time-to-digital conversion circuit based on FPGA
Abstract: This paper introduces a design method for high-precision time-to-digital conversion circuit based on FPGA. By using the on-chip phase-locked loop (PLL) and circular shift register, a high time resolution can be obtained with a low system clock and less logic resources are occupied. It can be used as an ind
[Embedded]
Design of high-precision time-to-digital conversion circuit based on FPGA
Design of TV aiming and viewing system based on DSP and FPGA
The electronic derotation system introduced in this paper uses Altera's StratixII series FPGA chip and ADI's ADSP2183 as the core, which can meet the system's requirements for function, real-time performance and accuracy. System principle and basic structure The block diagram of the TV sighting system is s
[Embedded]
Design of TV aiming and viewing system based on DSP and FPGA
FPGA microcontroller shows you how to implement multi-machine serial communication network
With the development of electronic technology and EDA technology, FPGA technology has been more and more widely used in the field of electronic design with its unique advantages. FPGA has the advantages of high integration, small size and low power consumption, and it also has user programmable capabilities. The use o
[Power Management]
FPGA microcontroller shows you how to implement multi-machine serial communication network
Latest Embedded Articles
Change More Related Popular Components

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

About Us Customer Service Contact Information Datasheet Sitemap LatestNews


Room 1530, 15th Floor, Building B, No.18 Zhongguancun Street, Haidian District, Beijing, Postal Code: 100190 China Telephone: 008610 8235 0740

Copyright © 2005-2024 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号