Design of LCD Controller Based on FPGA and Verilog

Liquid crystal displays are widely used in mobile communication terminals, portable computers, GPS satellite positioning systems and other fields due to their low voltage, low power consumption, large display information volume and small size, and have become the most widely used display device. Liquid crystal display controllers, as the core components of liquid crystal drive circuits, are usually composed of integrated circuits, which realize liquid crystal display by providing timing signals and display data for liquid crystal display systems. This design is a liquid crystal display controller based on FPGA (field programmable gate array). Compared with integrated circuit controllers, FPGAs are more flexible and can change timing signals and display data for different liquid crystal display modules. The integration, complexity and area advantages of FPGAs make them an increasingly attractive and cost-effective alternative to ASICs. This paper uses Xilinx's SpananIII series XC3S200 device and uses the hardware description language Verilog to design a liquid crystal display controller, which replaces the dedicated integrated circuit to drive and control LCDs.

1 Functional analysis and design requirements

The liquid crystal display module (LCM) uses Shenzhen Topology Micro LM2028, STN graphic dot matrix liquid crystal display module, 5.7in, 320×240 dot matrix, logic voltage input of 3.0~5.0V, 4-bit control interface, with row and column drive circuit, white LED backlight source. Table 1 is the pin function description of the liquid crystal display module.

The scanning mode of the liquid crystal display is line-by-line scanning. When a row is selected, the signals of each column in this row are added to the column at the same time and maintained for a scanning row time. After the maintenance time of this row ends, the next row is selected, and the display voltage of the next row is applied to each column electrode at the same time.

The column driver logic circuit is composed of a shift register and a latch. Under the action of a display data shift pulse signal CP, a group of display data (4 bits) is shifted into the register and maintained. When the next CP arrives, the first bit of display data in the shift register is shifted to the second bit. In this way, under the action of 80 CP pulses, after a row of display data is stored in the register, the register is connected to the latch in parallel. Under the action of the latch pulse LP, the row data is latched into the latch and output to the column electrode. The interval of the latch pulse LP is one row cycle, and the row shift pulse interval is also one row cycle, so the two are consistent. [page]

The frame scan signal FLM is the line selection signal, and its pulse width is one line time. Under the action of the line shift pulse LP, it is stored in the shift register and shifted line by line. A high level is output at the last line of a frame, indicating the beginning of the next frame. M is the liquid crystal display AC drive waveform signal, that is, the polarity of the waveform is changed once a frame to prevent the liquid crystal from unidirectional distortion. A more detailed timing relationship is shown in Figure 1.

2 Design and Implementation

2.1 Overall Design of LCD Controller

The refresh rate of the LCD display in this design is 70Hz, each frame period is 14.28ms, each row period is 60μs, the frequency of the clock signal CP is 2 MHz, and the time to input a row of data into the column shift register is 40μs, so a 20μs blank time is designed for each row.

The principle of the LCD controller system is shown in Figure 2. The clock module is customized using Xilinx's Coregen IP tool. The digital clock manager DCM module divides the FPGA 50 MHz clock signal CLK_IN 25 into a 2 MHz controller clock signal CLK. DCM uses digital delay phase-locked loop technology to eliminate the shift of the clock phase and provide a more stable clock signal than self-division to meet the control system requirements. The CONTROLLER module provides LCM with control signals CP, LP, FLM, M, DISPOFF that meet the timing requirements shown in Figure 1, and synchronously generates the SRAM read address ADDRA[14:0].

SRAM is a memory module. In order to increase the data flow speed of the input LCD, a 32K×4-bit port memory is designed, which can realize read/write at the same time and realize the conversion of data format. The 8-bit data input by the host MCU is converted into 4-bit data input to the LCM column driver; the B port is connected to the host MCU by MCU_INTERFACE, and the MCU microcontroller writes the display data into the memory SRAM. Among them, ADDRB[13:0] controls the 16K×8-bit write address, DINB[7:O] is the write data, WEB is the write valid control, and CLKB is the write clock; the A port is controlled by the CONTROLLER module to control the read address ADDRA[14:0], the read clock CLKA is controlled by the system clock signal CLK, and DOUTA[3:0] writes the data to the LCM column driver. [page]

2.2 Control module design

The control module CONTROLLER is designed using the Verilog hardware description language by applying the state machine method. CLK is a 2 MHz input clock signal. LP and the internal control signal DEN are generated by state machine 1, FLM is generated by state machine 2, and M is generated by state machine 3. The CP signal and ADDRA[14:0] are obtained according to the CLK and DEN signal control. State machine 1 has 3 states: State 1, LP is 0, DEN is 1, and it turns to state 2 after 80 CLK pulses; State 2, LP is 1, DEN is 0, and it turns to state 3 after 1 CLK pulse; State 3, LP is 0, DEN is 0, and it turns to state 1 after 39 CLK pulses. State machine 2 has 2 states: State 1, FLM is 1, and it lasts for 1 LP cycle time, that is, 120 CLK pulses; State 2, FLM is 0, and it lasts for the remaining 239 LP cycles, that is, 28,680 CLK pulses. State machine 3 has 2 states, State 1, M is 1. It lasts for 1 FLM cycle, that is, 28800 CLK pulses; state 2, M is 0, and it also lasts for 1 FLM cycle. Since the CP signal and ADDRA contain blank signals, they are obtained from the internal control signal DEN and the clock signal CLK. The following is the initialization part of the design source code:

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3 Simulation, download test analysis

After completing the controller design in the ISE6.3 environment, the simulation test was completed in the MODELSIM6.1b environment. The waveform is shown in Figure 3.

The simulation waveform results meet the design requirements. After the simulation is completed, after comprehensive implementation, the programming file is generated and the Xilinx FPGA device XC3S200 is programmed by downloading the software, and the Tektronix logic analyzer TLA721 is used for analysis and testing. The results are shown in Figure 4.

The timing relationship between the control signals in Figure 4 fully meets the design requirements. It is measured that a CP pulse period is 500ns, and there are 40 CP pulse periods of about 20μs blank signals at the end of each line; the LP period is 60μs, and the high level duration is 500ns, that is, one CP period; the FLM period is 14.28 ms, about 70 Hz, and the high level duration is 60μs, that is, one LP period. The test results show that the designed liquid crystal controller fully meets the requirements of LCM for control signals.

Conclusion

The method of designing LCM controller using hardware description language Verilog has the characteristics of reducing circuit board size, easy integration into on-chip system, reducing system volume, convenient modification, adaptability to different liquid crystal displays, etc. It has good reusability; it is also the basis for the subsequent development of other types of liquid crystal display controllers.

After the LCD display controller and MCU form a display system, the MCU writes the display data into the SRAM, and the controller reads the display data and sends it to the LCM synchronously with the control signal, thus realizing the graphic display well. This shows that the LCD display controller has successfully replaced the traditional ASIC LCD controller and has a good application prospect.