FPGA Implementation of Despreading and Synchronization Technology for DS/FH Hybrid Spread Spectrum Receiver

In the DS/FH hybrid spread spectrum communication system, digital down-converters, correlation accumulators and code generators are required to complete down-conversion, correlation despreading and other operations. Dedicated chips are usually used to complete these functions, which increases the size of the system and makes it difficult to miniaturize. Modern EDA (electronic design automation) tools have broken through the limitations of only being able to perform PCB layout design or circuit function simulation and pure software in the early days. With the goal of ultimately achieving a reliable hardware system, they are equipped with all the tools for automatic system design, such as various commonly used hardware description language platforms VHDL, Verilog HDL, AHDL, etc.; they are equipped with a variety of compatible and mixed logic description input tools, such as hardware description language text input methods (including Boolean equation description methods, schematic description methods, state diagram description methods, etc.) and schematic input methods, waveform input methods, etc.; at the same time, they are also equipped with high-performance logic synthesis, optimization and simulation tools. FPGA was developed on the basis of logic devices such as PAL and GAL. Compared with PAL, GAL, etc., FPGA is larger in size and more suitable for timing, combinational and other logic circuit applications. It can replace dozens or even hundreds of general-purpose IC chips. FPGA has the characteristics of programmability and easy design changes. The description of the hardware connection relationship inside the chip can be stored in the download chip. Therefore, when the programmable gate array chip and peripheral circuits remain unchanged, the download chip can be replaced to achieve new functions. Soon after the advent of FPGA chips and their development systems, they have attracted widespread attention and general popularity among electronic engineering designers around the world [1~5]. This paper mainly discusses the implementation structure of the despreading and synchronization process of a DS/FH hybrid spread spectrum receiver based on coded spread spectrum. The APEX20K200RC240-1 device of ALTERA Company and its development platform Quartus II are used to implement the core of the hybrid spread spectrum receiver - the despreading and synchronization module.

1 FPAG Design of Despreading Module of Hybrid Spread Spectrum Receiver

The despreading module is the core of the hybrid spread spectrum receiver. This module realizes the despreading of the received signal, and mainly includes a digital down-converter, a numerically controlled oscillator (NCO), a code generator, a correlation accumulator, and a pseudo-code phase shift circuit. Usually, each module uses a dedicated chip. Using FPGA to integrate these functions into a chip greatly reduces the size of the receiver and facilitates the miniaturization and integration of the system. The following introduces the FPGA implementation structure of each part of the module.

1.1 Numerically Controlled Oscillator (NCO)

The digital controlled oscillator is an important component of the despreading module. It is mainly used to provide an accurate clock signal for the code generator, thereby realizing the capture and tracking of the received signal. The code generator consists of a phase accumulator and a lookup table. If a 40-bit accumulator is used, for a certain frequency control word A, the relationship between the output frequency fout and the input frequency control word A is:

fout=fclkA/240

Where fclk is the system clock. As long as the size of the control word A is changed, the output frequency fout can be controlled. The minimum step size Δf of fout change is determined by the data width of the accumulator. If the data width is 40 bits, then:

Δf=fclk/240

Using the above principle, the required frequency can be obtained through accurate frequency division. The schematic diagram is shown in Figure 1.

In Figure 1, the frequency control word A is written by DSP. Considering the internal storage resource limitation of FPGA, the high eight bits of the 40-bit phase accumulation value result[39. . 0] are taken as the input of the look-up table LUT (look-up table). The look-up table is composed of ROM and stores the sampling values ​​corresponding to each phase. When the input end of the look-up table is a certain phase phase, the corresponding sampling value is output. If the output data width is 6 bits and the output signal format is a cosine signal, the LUT output is [6]:

out[5． ． 0]=31×cos(360×(phase+0.5)/256)°+32

If the ROM's parallel 6-bit out[5. . 0] is taken as the output, the output signal is a digitized cosine signal with 256 points sampled per cycle; if the highest bit out[5] is taken as the output, the output is a frequency-divided signal of the system clock. [page]

1.2 Digital Down Converter

The digital down-converter down-converts the intermediate frequency signal obtained by A/D sampling, removes the intermediate frequency, and obtains the baseband signal. The local NCO is used to generate sine and cosine signals with the same frequency as the input intermediate frequency signal, and complex multiplication is performed with the input signal. Then, the operation result is low-pass filtered to complete the down-conversion operation of the intermediate frequency signal. In the orthogonal sampling mode, the two A/D converters provide orthogonal inputs IIN and QIN, and the complex multiplier outputs IOUT and QOUT of the digital down-converter are:

IOUT=IINcos(ωt)-QINsin(ωt)

QOUT=IINsin(ωt)+QINcos(ωt)

The local oscillator signal, complex multiplier, and low-pass filter are all digitally designed. The digital down-converter uses the APEX20K200RC240-1 device of ALTERA. The typical gate count of this device is 200,000, with abundant logic units and RAM units. The macro modules provided by the development platform Quartus II, such as lpm_mult (multiplier macro module), lpm_rom (ROM macro module), lpm_add_sub (adder macro module), etc., bring great convenience to the design. The schematic diagram of the digital down-converter is shown in Figure 2.

The numbers in Figure 2 represent the data width of the corresponding module. The filter module is a second-order low-pass filter that filters out the high-frequency components after mixing. In some dedicated digital down-conversion devices such as STEL-2130, the order of the filter is programmable and different orders can be set as needed to obtain different filtering effects. Considering the resource issues of FPGA, the order of the filter is set to a fixed second order. The relationship between the filter input x[n] and the output y[n] is:

y[n]=x[n]+x[n-1]

y[n-1]=x[n-2]+x[n-3]

The low-pass filter adds two adjacent input data as output, that is, every two input data correspond to one output data, and the input data clock beat is twice the output data clock beat.

The data after low-pass filtering is processed by a sliding window, which selects and outputs the input data to dynamically adjust the size of the correlation peak. When observing the correlation peak during the capture process, by adjusting the sliding window, correlation peaks of different amplitudes can be obtained. The selection control end is determined by the DSP writing control word, and the structure is shown in Figure 3. The sliding window control logic relationship is:

CASE sel[] IS

WHEN 0=> dataout =datain[7. ． 0];

WHEN 1=> dataout =datain[8. ． 1];

WHEN 2=> dataout =datain[9. ． 2];

WHEN 3=> dataout =datain[10. ． 3];

WHEN 4=> dataout =datain[11. ． 4];

WHEN 5=> dataout =datain[12. ． 5];

WHEN OTHERS => dataout =datain[12. ． 5];

The sign extension is to keep the width consistent with the subsequent related accumulator data. The sign bit extension must be consistent with the sign of the highest bit of the input data.

[page]

1.3 Correlation Accumulator

The correlation accumulator completes the correlation accumulation operation between the local pseudo code and the received signal, and the result of the operation is sent to the DSP to complete the capture and tracking of the pseudo code. If the pseudo code length is 256 bits and half-chip sliding is adopted, 512 accumulation operations are completed in one code period. If the serial sliding correlation capture method is adopted, the time required to traverse all code phases is 512 code periods, that is, the maximum time required for capture is 512 PN code periods. Due to the development of programmable logic devices, there are sufficient hardware resources to complete parallel operations. Here, a serial/parallel mixed capture method [6][7] is adopted, using 8-way correlation accumulators, each of which is divided into three groups: leading, current, and lagging. The phase difference between each group is half a chip, and the phase difference between each group is 64 half chips. In this way, only 64 half-chip phases need to be slid to traverse all pseudo code phases, and the time required to complete capture is shortened to one eighth of the original. Data demodulation is completed by another 4 groups of correlation accumulators. Since the phases of the synchronization pseudocode at the transmitting end are strictly aligned with the data pseudocode, in the receiving module, after completing the synchronization pseudocode capture and tracking, the obtained phase information is directly used in the data demodulation correlator to correctly demodulate the data.

The tracking of synchronous pseudocode adopts the lead-lag delay locked loop (DPLL), and each correlator includes 3 groups of accumulators. A total of 28 groups of correlation accumulators are used for acquisition tracking and data demodulation. The structure of each group of correlation accumulators is exactly the same, divided into I and Q paths, and the accumulation operation is performed separately. After completing 512 accumulation operations, the data is read by the DSP. The structures of the I and Q paths are exactly the same, and the schematic diagram of one path is shown in Figure 4.

The relevant accumulator consists of an 18-bit adder and subtractor, latch 1 and latch 2. data[7． ． 0] is the input data after down-conversion, and PN CODE comes from the code generator. As the control terminal, the low level completes the addition operation, the high level completes the subtraction operation, the DP rising edge latches the data, and the falling edge completes an accumulation operation. When the accumulation operation is completed, the CLR signal is cleared and the result is stored in latch 2. The falling edge of CLR is valid. Latch 1 outputs the OV signal as the overflow flag, and latch 2 outputs the accumulation result out[16． ． 0]. The highest bit of the input and output terminals is the sign bit.

1.4 Local code generator and code phase shift circuit

The local code generator is used to generate a local PN code, which is then correlated with the received signal. Since the transmitter uses coded spread spectrum modulation, the received signal contains both a synchronization PN code and a data PN code. Corresponding to the received signal, the local should also generate a corresponding PN code for synchronization and demodulation of data.

The local PN code generator is fully implemented using FPGA, and programmable registers and external interfaces are set. The DSP can preset the PN code length through the interface. The 1024-base counter circuit is used to generate the input address of the ROM. The ROM is implemented by the internal RAM resources of the FPGA, using the APEX20K200 device of ALTERA. The internal programmable RAM capacity of the device is 106496 bits, which can fully meet the design requirements. The local PN code adopts the half-chip sliding method, and the PN code inside the ROM is also stored in the half-chip method. If the code length is 256, after using the half-chip storage method, each group of PN codes needs to store 512 bits of data, and the corresponding ROM has a 9-bit address line drive output. The drive clock is twice the PN code clock. In the actual design, 8 groups of PN codes are stored in the PN code generator, but only five groups are used, one group is used for synchronization, and the other four groups are used for demodulation data. The ROM input address is generated by the 1024-base counter. In fact, only a 512-base counter is needed to obtain the ROM input address. Considering the scalability, a variable counter with a maximum counting capacity of 1024 is used here. The output phase of the PN code can be easily adjusted by rewriting the register value through the DSP-FPGA interface.

The main function of the pseudo code shift circuit is to shift the PN code generated by the code generator to obtain different phases of the pseudo code. The capture and tracking process uses a total of 8 channels and 24 groups of related accumulators. Each channel is divided into three groups: leading, current, and lagging. The PN codes at the input of these three groups of accumulators differ by half a chip phase. The difference between each adjacent two channels in the 8 channels of related accumulators is 64 half chips. The code generator outputs 5 groups of PN code sequences (group 0 to group 4), corresponding to the synchronous pseudo code and 4 groups of data pseudo code. The 5 groups of pseudo codes are all passed through a 512-level shift register. The 0th group of PN code is used as the synchronous code, and its 0, 1, and 2 phases are taken as the inputs of the leading, current, and lagging three groups of related accumulators of the first channel; the 64, 65, and 66 phases are used as the inputs of the leading, current, and lagging three groups of related accumulators of the second channel, and the rest of the channels are analogous. When the capture is completed, the captured synchronous PN phase needs to be switched to the data demodulation related accumulator. For example, assuming that the current channel of the second group of correlation accumulators is captured, the PN code phase of the correlation accumulator used for demodulating data should be consistent with the PN code phase of the current channel of the second group of correlation accumulators. The data pseudo code phase switching is achieved by the DSP memorizing the phase of the capture channel and then controlling the multiplexer to select the phase.

2 FPGA Implementation of Synchronization Module

The synchronization module is composed of bit synchronization and frame synchronization circuits, which mainly realize the detection and extraction of information data, identify the frame header position of a frame of information data, and realize the synchronization of frequency hopping pattern. The synchronization of frequency hopping pattern adopts the waiting search synchronization method. At the beginning, the frequency synthesizer of the receiving end stays at a single frequency point fi', waiting for the frequency fi of the transmitter. When the frequency of the transmitter jumps to fi, the local frequency fi' of the receiving end is mixed with the transmitted frequency fi, and the intermediate frequency fIF is output. After the DSP completes the despreading and demodulation operation, the obtained serial data stream is sent to the bit synchronization and frame synchronization circuit. The feature word is extracted from the data stream, and a complete frame of data can be obtained, thereby determining the position of the frame header, that is, the frequency conversion moment, thereby controlling the synchronous jump of the frequency synthesizer of the receiving end and the frequency synthesizer of the transmitting end to realize the synchronization of frequency hopping pattern. Due to the use of coded spread spectrum modulation, every two information bits of the transmitting end are encoded into one of the four PN codes in one PN code cycle. Therefore, the receiving end compares the maximum value of the accumulated results of the four groups of data correlation accumulators in each PN code cycle, and then decodes them into corresponding information data. The information data is sent to the synchronization circuit for Barker code matching correlation, extracting the valid information bits, and controlling the frequency hopping timing to complete the frequency hopping synchronization. The principle of the synchronization module is shown in Figure 5.

In each PN code cycle, 4 groups of data demodulation correlation accumulators demodulate 2-bit information data. The 2-bit information data is sent to the synchronization circuit at a rate of 9.6kHz. The synchronization circuit first converts the information data into parallel and serial data, transforming the 9.6kHz, 2-bit data stream into a 19.2kHz, 1-bit data stream. The converted data stream is then converted into a 19.2kHz, 32-bit parallel data stream. According to the signal format, each frame of data is 32 bits, and the corresponding 13-bit Barker code has a fixed position in a frame of data. Therefore, the 13-bit data bits at the corresponding position in each frame of data are extracted and correlated with the local Barker code for matching operations. The result is compared with the threshold value. If it meets the threshold setting, an interrupt output is generated to notify the external device to read the corresponding data. [page]

3 Experimental Results

The technical indicators of the system are: information data rate 4.8kbps, bit rate 19.2kbps. Frequency hopping rate 600hop/s, 20 frequency hopping points, frequency hopping bandwidth 68MHz, 32bit spread spectrum code period per hop 256, code rate 4.9152MHz. The experimental results were observed using a TEKTRONIX 2221A digital storage oscilloscope. Figures 6 to 9 show the test results of each test point of the FPGA.

The first group of waveforms in Figure 6 is a 256-code-long local receiving synchronization pseudo code stream, and the second group is a frequency hopping frame synchronization signal. The pseudo code phase corresponding to this signal is the phase during despreading and frequency hopping synchronization. The first group of waveforms in Figure 7 is a receiving data stream, and the second group of waveforms is a transmitting data stream. The transmitting data frame format is 00000000011111001101010000000000, the frame synchronization code is a 13-bit Barker code 1111100110101, and the 8-bit information data is 00000000. It can be seen from Figure 7 that the receiving end data is the same as the transmitting end, but lags behind the transmitting end. This is caused by the transmission delay. The first group of waveforms in Figure 8 is the receiving serial data, and the second group is a frequency hopping frame synchronization signal. The falling edge of this signal corresponds to the start of a frame of data, which controls the frequency synthesizer to perform frequency conversion. The first group of waveforms in Figure 9 are the transmitting frequency hopping frame signals, and the second group are the receiving frame synchronization signals. The rising edge of the receiving frame signal is aligned with the falling edge of the transmitting frequency hopping frame signal, and the signal width is greater than the transmitting end signal. This is because the updata signal that controls the frequency synthesizer to perform frequency conversion requires a certain width.

Despreading and synchronization are the key to correct data demodulation of DS/FH hybrid spread spectrum receiver. The FPGA design realizes the functions of multiple dedicated chips, greatly reducing the size of the receiver and facilitating the miniaturization and integration of the system. Algorithms such as capture and frequency hopping synchronization are implemented in hardware, which speeds up the capture and tracking speed. The programmability of FPGA makes the circuit design more flexible and gives the system the characteristics of a "soft" receiver. The experimental results show that the FPGA system design is correct and feasible.