Synopsys' flagship Fusion Compiler product helps customers achieve more than 500 tapeouts

Synopsys' Flagship Fusion Compiler Helps Customers Achieve More Than 500 Tapes, Extending Industry Leadership

Help customers improve performance by 20%, reduce power consumption by 15%, and reduce area by 5%

summary:

•The tape-out range covers 40nm to 3nm designs in market segments such as 5G mobile, high-performance computing, artificial intelligence, and hyperscale data centers.

•Many leading semiconductor companies leverage Synopsys' Fusion Compiler for tight production deployment to further achieve industry competitive advantage.

MOUNTAIN VIEW, Calif., Dec. 3, 2021 -- Synopsys, Inc. announced that customers have achieved more than 500 tapeouts using its Fusion Compiler™ RTL-to-GDSII solution since its general release in 2019, extending Synopsys' leadership in digital design. Leading semiconductor companies in high-growth verticals such as high-performance computing (HPC), artificial intelligence (AI), and 5G mobile have successfully taped out their designs at 40nm to 3nm process nodes using Fusion Compiler.

How to achieve strict performance, power, and area (PPA) targets within a tight time frame and at advanced process nodes is a severe challenge facing many developers at this stage. With its unified architecture and optimization engine, Synopsys Fusion Compiler can help developers achieve accurate PPA indicators at the sign-off level and greatly reduce design iterations and late-stage accidents. It is estimated that compared with other solutions in the industry, the Fusion Compiler solution can help customers achieve an average of 20% performance improvement, 15% power reduction, and 5% area reduction.

"We have extended our industry leadership through tight production deployment of Synopsys' Fusion Compiler solution, which has resulted in superior quality of results, including significant utilization improvements and faster time-to-market," said Ilyong Kim, vice president of the Design Technology Team at System LSI Business at Samsung Electronics. "Its unique single data model and unified engine, along with built-in signoff-level timing analysis, parasitic extraction, and power analysis, have helped us reduce design iterations, which has set us apart from other industry solutions. We have seen the benefits of Fusion Compiler in multiple successful design tapeouts, and we are currently expanding our deployment to use Synopsys' latest machine learning technologies to further deepen our customer-centric differentiation."

"Kioxia is a leading memory supplier to the semiconductor industry and is at the forefront of producing high-performance memory controllers," said Kazunari Horikawa, senior manager of Design Technology Innovation Division at Kioxia Corporation. "We have been able to significantly improve process efficiency by implementing a complete Fusion Compiler design flow with Synopsys. In addition, with the test fusion technology of Synopsys' TestMax product, we were able to shift our design methodology left and achieve a 40 percent reduction in power consumption and 10 percent reduction in area in our latest tapeout, further extending our leadership in the industry. We look forward to working with Synopsys to further improve productivity with the Fusion Compile solution."

Production-proven and scalable data models help customers achieve predictable quality of results

Fusion Compiler is the industry's only RTL-to-GDSII product that supports a single data model and golden signoff standard. It uses a highly scalable unified data model and includes analysis technology from the industry's golden signoff tools. These features are all packaged in an integrated environment to deliver a uniquely customized flow with predictable quality of results (QoR) and signoff relevance. In addition, the product's unique architecture is further enhanced by "ubiquitous machine learning" technology, enabling even higher levels of productivity and QoR.

"Our customers continue to face pressure to deliver solutions to new markets within tight timelines. With Fusion Compiler, they are able to accelerate their time to market while delivering differentiated PPA," said Sanjay Bali, vice president of marketing and strategy for the Digital Enablement Group at Synopsys. "With over 500 tapeouts achieved by our customers using Fusion Compiler, this reaffirms the need for vertically integrated RTL-to-GDSII solutions that can achieve the desired PPA targets."

Fusion Compiler is the core of Synopsys' Fusion Design Platform™, the industry's first AI-enhanced cloud-based design solution. Fusion Design Platform redefines the boundaries of traditional EDA tools such as logic synthesis, place and route, and signoff verification. It uses machine learning to accelerate computationally intensive analysis, improves decision-making through predictive results, and achieves better results by learning from past experience.

At the recent Synopsys Digital Design Technology Symposium, customers including AMD, Arm, and MediaTek detailed their design experiences using Fusion Compiler and Fusion Design Platform.