Design of Multi-channel HDLC Transceiver Circuit Based on FPGA

The HDLC (High Level Date Link Control) protocol is one of the most widely used protocols in the field of communications. It is a bit-oriented high-level data link control procedure with powerful error detection, high efficiency and synchronous transmission. There are many dedicated HDLC chips on the market, but most of these chips have complex control and a limited number of channels. On the other hand, the use of dedicated chips will effectively increase the PCB area, which is not conducive to the miniaturization of equipment and brings high costs and other problems.

FPGA can process signals of any data width, and the internal functional modules can be processed in parallel. Therefore, the use of FPGA technology to design the HDLC protocol controller can balance the load of the entire system, realize a multi-channel high-performance HDLC protocol controller, and ensure the reliability of communication. At the same time, it also has the advantages of short design and development cycle, low design and manufacturing cost, and real-time online inspection, so it is widely used in special chip design. In this design, Altera's EP2C70F672C8 chip is used to implement the HDLC protocol controller.

1 Introduction to HDLC Protocol

In the HDLC communication mode, all information is transmitted in the form of frames. The HDLC frame format is shown in Table 1.

(1)Sign word.

The HDLC protocol stipulates that all information transmission must start with a flag word and end with the same flag word, which is 01111110. The start flag and the end flag constitute a complete information unit, called a frame. The receiver can detect the start and end of the frame by searching for 01111110 to establish frame synchronization. In the idle period between frames, flag words can be sent continuously to fill.

(2) Information segment and “0” bit insertion technology.

The information length of the HDLC frame is variable, and any binary information other than the flag word can be transmitted. In order to ensure that the flag word is unique, the sender uses the "0" bit insertion technology when sending information, that is, when the sender sends all information except the flag character (including the check bit), as long as it encounters 5 consecutive "1", it automatically inserts a "0"; conversely, when the receiver receives data, as long as it encounters 5 consecutive "1", it automatically deletes the subsequent "0". The "0" bit insertion and deletion technology also makes HDLC have good transmission transparency, and any bit code can be transmitted.

(3) Address segment and control segment.

The address field is 8 bits and can be extended in multiples of 8 to identify the stack address that receives the frame. The control field is 8 bits and the sender's control field is used to indicate the category and function of commands and responses.

(4) Frame check.

HDLC uses 16-bit cyclic redundancy check code (CRC-16) for error control. Its generating polynomial is x16+x12+x5+1. Error checking refers to the CRC cyclic redundancy check of the content of the entire frame, that is, the error code within the error correction range is corrected, and the error code within the error correction range is checked, but cannot be corrected. The flag bit and all "0" inserted according to the transparent rule are not within the range of verification.

2 FPGA Implementation of HDLC Protocol

In order to ensure that the remote control and telemetry platform meets the mission requirements of high-speed communication, multi-channel reception and transmission, and easy functional expansion and configuration, the central controller adopts an integrated design with a high-performance ARM7 as the CPU data processing core and an FPGA-designed serial communication controller to transmit and receive multi-channel HDLC data.

FPGA receives and stores digital quantities from 8 independent channels such as integrated processors according to the HDLC protocol. The system first converts the external input HDLC data stream from RS485 electrical characteristics to TTL level. In this process, optocouplers are used for isolation to avoid mutual interference with external devices, and the power supply of RS485 chip and optocoupler devices uses independent 5 V and 5 V ground supplied by electricity. The overall structure block diagram of HDLC protocol is shown in Figure 2. Each control module consists of functional modules such as clock control, encoding/collision detection, transmission and reception FIFO. In the transmission direction and reception direction, there is a 128-bit FIFO for data buffering between the serial channel and the CPU bus interface. Transmission is the reverse process of reception. Here, HDLC data reception is used as an example to illustrate.

The principle of FPGA serial communication controller receiving HDLC data is as follows: first, the message field and the additional status field of the received data frame are moved in, and then the destination address in the received frame is identified according to the selected addressing mode to confirm whether the sending address of the data frame is the device (station address = 77H). If it is the data frame of the device, the data is received and stored in the FIFO. When the receiving data frame is finished, an interrupt signal is sent to the ARM system to request to receive HDLC data. [page]

The data frame whose destination address is not this device will be discarded. The flow chart is shown in Figure 3.

3 Experimental Results and Analysis

First, a pair of HDLC data transceiver circuits are implemented in FPGA, and the transceiver circuits are simulated and tested. By generating relevant data files as the data source of HDLC in the Matlab development environment, directly calling them in the test file of ModelSim SE 6.1, and finally comparing the simulation results with the data source generated by Matlab, satisfactory results can be obtained. The test code coverage of the simulation is 100%, and the simulation results and the data source are completely consistent, which can confirm the correctness and good reliability of the circuit. Figure 4 and Figure 5 are the simulation diagrams of the HDLC data transceiver module in ModelSim SE 6.1.

In order to rationally utilize the logic resources inside the FPGA, a series of layout and routing constraints are imposed on the design: (1) From the previous demonstration, it can be seen that the design contradiction is mainly concentrated on the resource consumption. The optimization target of all modules is positioned as "Area". Except for FIFO, other modules are planned together; (2) FIFO is divided into independent modules; (3) The global clock is bound to the Global resource, and the derived clocks in the parallel/serial and serial/parallel modules are set as multi-cycle paths according to the relationship with the global clock.

The stability and reliability of actual data transmission and reception are also related to the board, temperature, etc. After the simulation is completed, the board is wired, the specific transceiver circuit is electrically connected, and the loopback test method is performed, that is, the data output by the transmitter is received by the receiver for testing. At room temperature, after 30 hours of long-term operation test, the received and sent data were compared, and no packet loss or error was found. From the test results, it can be seen that the HDLC transceiver circuit is stable and reliable. High and low temperature experiments were not carried out due to limited conditions. The temperature characteristics of the board can be roughly inferred from the temperature characteristics of the device, which will not be discussed here.

4 Conclusion

Aiming at the requirements of a remote control and telemetry platform, this paper proposes a multi-channel HDLC transceiver circuit design based on FPGA, and uses Altera's P2C70F672C8 chip to implement it. At present, the board that implements the circuit has been debugged and successfully applied to the whole machine test. Practice shows that the circuit has the advantages of simple implementation, high reliability, and flexible use, and has certain promotion value.