Design of General FPGA Signal Processing Board Based on CPCI Bus

With the continuous development of radar signal processing technology and the demand for radar technology in modern national defense, the system's requirements for radar signal processing are becoming higher and higher, and more and more massive data needs to be processed in real time. Advanced radar signal processing equipment not only requires high performance and diversified functions, but also requires the development and equipment cycle of signal processing equipment to be short, and to keep pace with the international advanced level. Therefore, it is necessary to develop a reconfigurable and scalable general signal processing system that can modularize, standardize and generalize radar signal processing. In this way, on the one hand, hardware expansion can be used to adapt to changes in the scale of signal processing, and on the other hand, flexible software programming can be used to implement various signal modes and various complex algorithms. FPGA has more advantages than DSP in radar signal processing, which is mainly reflected in the following points: (1) The implementation of digital signal processing algorithms by specially designed hardware circuits can maximize the use of its parallelism, and can achieve much higher computing performance than the serial operation of DSP processors, and has stronger real-time performance; (2) Some new FPGAs can implement a large amount of on-chip RAM, which can realize data transmission and storage operations at high data rates that traditional DSP systems cannot achieve; (3) Lower power consumption. In this paper, a general FPGA signal processing board based on CPCI bus is designed by using Ahera's latest high-end FPGA StratixⅢ with the best performance, maximum density and lowest power consumption, and it is actually applied in a radar system.

1 System Implementation

The system can process 8 analog signals or 8 digital signals at the same time. The two working modes are adaptively selected through external control signals. The system block diagram is shown in Figure 1.

The EP3SE1 10F1 152C4 of the StratixⅢ series of high-end FGPA products of Altera's 65 nm process is selected. StratixⅢ has improvements in four aspects, including power consumption, performance, ease of use and cost. Among them, the programmable power technology can significantly reduce power consumption while meeting high performance requirements. Compared with the previous generation Stratix II devices with 90 nm process, the hardware architecture improvement and Quartus II software improvement have reduced the power consumption of StratixⅢ by 50%, while improving the performance by 25%, and the density is twice that of the former. Each EP3SE110F1 152C4 simultaneously processes two signals in real time. It contains 448 18×18 fixed-point hardware multipliers, 85,200 adaptive logic units, and 8 MB of embedded RAM. Such rich hardware resources make it possible to use FPGA to realize radar signal processing. The overall structure of the system hardware is shown in Figure 2.

8 analog signals are sent to FPGA through 8 A/Ds, 8 digital signals are sent to FPGA through CPCI interface for signal processing, and control signals are sent to FPGA through CPCI interface. The result of signal processing is sent to CPCI interface through PCI9054, and the data is directly analyzed and processed on the computer. The data is sent to the back-end through CPCI interface for signal processing, and observed and analyzed through two D/A. [page]

2 Application of General FPGA Signal Processing Board in a Radar System

2.1 Universal signal processing board realizes digital down-conversion

Digital down-conversion is one of the key technologies in radar signal processing. Low-pass filtering is usually used to achieve digital down-conversion. The low-pass filtering method includes three parts: orthogonal interpolation, low-pass filtering and sampling. The algorithm block diagram of digital down-conversion is shown in Figure 3. After A/D orthogonal sampling, the analog signal is point-multiplied with the cosine module and the sine module to achieve orthogonal transformation. Then the I and Q data are respectively passed through the low-pass filter and finally sampled and output.

Figure 4 is a block diagram of the FPGA implementation of the digital down-conversion algorithm, which is mainly divided into three modules: data conversion module, FIR module and sampling module. The data conversion module implements multiplication operations. When external data comes in, different data is output according to different times, mainly including the original value, the inverse of the original value and 0.

The linear frequency modulation signal with a time-bandwidth product of 1 028 is input, and the system measures the I and Q waveforms, as shown in Figure 5.

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2.2 Universal FPGA signal processing board realizes large time-bandwidth product digital pulse compression

Digital Pulse Compression (DPC) processing refers to the pulse compression processing of the digital signal after the radar echo received by the radar receiver is sampled by A/D. The implementation of digital pulse compression can be divided into two types: time domain method and frequency domain method. Time domain processing refers to the convolution operation of the radar echo sequence x(n) and the coefficient h(n) of the matched filter. At this time, the output of the matched filter is

The signals and matching parameters involved in pulse compression are both complex numbers, so time domain processing is a complex convolution process, which is a multiply-accumulate (MAC) process.

For pulse compression systems, it is usually necessary to process linear frequency modulation signals and nonlinear frequency modulation signals. For linear frequency modulation and nonlinear frequency modulation signals, the matched filter coefficients can be designed to be symmetrical. By using the symmetrical FIR filter structure, the data is added before the data and coefficients are multiplied, and the multiplication operation is reduced by N/2 times, which greatly saves multiplier resources. The structural block diagram is shown in Figure 6.

Since the multiplier resources in FPGA are very valuable, in order to improve the utilization rate of multiplier resources, the time division multiplexing method is adopted. Consider using only one multiplier and performing time division multiplexing on it. In systems that do not require a high sampling rate, this structure can achieve practical and high cost performance. When designing the filter, the multiplexing times IV and sampling frequency of the multiplier are flexibly selected according to the actual situation. In the time interval from the end of the last addition operation to the start of this addition operation, the multiplier should complete N multiplication operations, that is, realize one convolution operation, so only one multiplier is needed, and its timing relationship is shown in Figure 7.

The time division multiplexing structure block diagram is shown in Figure 8.

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According to the speed grade of FPGA and the sampling frequency of data, the multiplexing times of multiplier is selected as 40. The frequency multiplication function of StratixⅢ's dedicated enhanced phase-locked loop (Enhanced PLL) is used to generate a clock with 40 times the sampling frequency as the clock of the multiplier, so that the multiplier can complete 40 multiplication operations in a stable data cycle. Every 40th order is regarded as a multiplication and accumulation unit, which is processed separately, and finally the results of each unit are summed. Each unit uses two 40-to-1 selectors, one selects the data involved in the operation, and the other selects the corresponding matching coefficient involved in the operation. The data and coefficient are sent to the multiplier at the same time. After the operation is completed, they are sent to the accumulator. After completing 40 multiplications, the accumulated result yk(n) is latched, and the yk(n) of each level is added to obtain the final pulse compression result y(n). Through time division multiplexing technology, the number of multipliers is only 1/40 of the original.

When a linear frequency modulation signal with a time-bandwidth product of 1 028 is input, the system measures the real part, imaginary part and modulus of the pulse pressure, as shown in Figure 9.

The measured data was imported into Matlab for analysis, and the main-to-sub ratio was obtained to be -42.38 dB, which met the system requirements, as shown in Figure 10.

The physical picture of the universal signal processing board is shown in Figure 11.

3 Conclusion

The general FPGA signal processing board based on CPCI bus designed in this paper has huge data processing capacity and high real-time performance. In practical applications, it realizes functions such as digital down-conversion and large time-bandwidth digital pulse compression. Without considering hardware design issues too much, as long as the design tasks are reasonably allocated to each processing unit on the board according to the resources on the general signal processing board, the reliability of the system can be improved and the design cycle can be shortened. This has important practical significance for radar signal processing systems with high data processing requirements, strong real-time performance, large data volume, and complex and changeable processing algorithms.