Keynote speech on breakthroughs in advanced chip manufacturing technology in the post-Moore era

At the World Semiconductor Conference held in Nanjing, Zheng Li, vice chairman of the China Semiconductor Industry Association, director and CEO of Changdian Technology, delivered a report entitled "Breakthroughs in Advanced Chip Manufacturing Technologies in the Post-Moore Era."

Zheng Li, Vice Chairman of China Semiconductor Industry Association, Director and CEO of Changdian Technology

I think the semiconductor integrated circuit industry is like other high-tech industries. There are some special terms in this industry, such as heterogeneous integration and the post-Moore's Law era mentioned by Academicians Mao and Wu Hanming. However, compared with other industries, the special terms in the integrated circuit industry are not as well-known as those in other industries, and everyone is concerned about them. For example, last year, the barber asked while shaving his head whether the lithography machine could not be bought in our country? In the first half of this year, people on the streets were talking about the problem of chip shortage and production capacity, especially the problem of automotive chip shortage. Those who have been exposed to and studied integrated circuits since the 1980s and studied integrated circuits when Moore's Law was in its infancy, now Moore's Law has entered the post-Moore era. On the one hand, we feel the changes, and on the other hand, we also feel a great sense of responsibility.
   

Today, I would like to share with you some thoughts from the perspective of chip manufacturing in the post-Moore era. Due to time constraints, I will only talk about two points: one is that advanced packaging is undergoing a dramatic transformation; the other is what kind of disruptive technological breakthroughs have occurred during this transformation.
   

1. The gorgeous transformation of packaging and testing technology in the post-Moore era
Let's first look at the word "packaging". Although I am the incumbent chairman of the Packaging and Testing Branch of the China Semiconductor Industry Association, I don't like the word "packaging" very much. I have been working in IDM for many years. In IDM, no matter the packaging process is called packaging, we call it wafers relative to the front-end, and the back-end is generally called back-end manufacturing. When the international industry chain is distributed, the front-end manufacturing and back-end manufacturing are put together, and the other several sectors are design, IP, equipment and materials.
   

The so-called advanced packaging has developed to the point where the key words are no longer just to take the chip and then put it in and seal it. It is indeed like that, put it in and then seal it. The key words now are that AMD has been soaring in the past few years by relying on back-end manufacturing technology, how to improve the integration of chips, and how to improve the high-speed interconnection in the package. So I said that when advanced packaging continues to move forward, the key to a gorgeous turnaround is that "sealing" and "packing" are no longer its determining factors, but highly integrated "collection" and highly interconnected "connection" have become the key to manufacturing.
   

The line width spacing of the rewiring layer has developed from 20 microns to 2×2, which is 10 times smaller. The wafer has gone from 28 nanometers to today's 5 nanometers and 3 nanometers, which is almost the same process. Ten years ago, the main chip of the mobile phone was made with the most advanced back-end manufacturing process. At that time, it was made with PUP packaging on the substrate. Today, it is made with fan-out process + GUP. The wafer node to be processed has changed from 28 nanometers to 5 nanometers, and the vertical height has changed from 1.6 mm to only 0.6 mm today. From the organic substrate at that time to the rewiring, the substrate is very scarce now, and it can be replaced by the opportunity-level IDU. The CPU and GPU mentioned by AMD just now have done very well in recent years. Now one is that the density of I/O has increased by 15 times, high-bandwidth memory has been integrated, and the distance between memory and GPU has also been shortened by 10 times. In a word, advanced packaging has achieved a qualitative leap in the stage of heterogeneous integration and microsystem integration in the process of technology advancement.
   

In terms of industry value positioning, we use the construction industry and the chip industry, especially the back-end manufacturing industry, to compare. The original traditional packaging is like a bricklayer, which does not belittle the meaning of bricks. Making bricks is not easy, but we are just making a brick. Advanced packaging is not just about wafer sealing and assembly. It requires complex wiring and reorganization, but this is only advanced packaging. It can be likened to using bricks to build a wall or even a house. It can be said to be the stage of advanced packaging. Today, heterogeneous integration and advanced packaging have reached the stage of microsystem integration. We are doing the same work as architects, not just building houses and walls. If you tell an architect that you are a bricklayer, will he agree? Today, if the work done by heterogeneous integration in back-end manufacturing is called packaging, we will not agree, and I think many friends in the industry will not agree, so this is its change.
   

This is not just a conceptual issue. The picture on the lower left is a screenshot of AMD. It is very shocking. It was announced at the conference last week that the density of 3D chipled integration is 300 times higher than that of 2D chipled integration, and 15 times higher than that of the original 3D solution using Micro for integration. Not only AMD, but also TSMC and Intel, international leading companies are actively deploying heterogeneous integration, and are working hard on semiconductor back-end technology to achieve one problem of integration and the other problem of high-density interconnection. Indeed, in the post-Moore's Law era in the industry, everyone continues to improve chip integration in different ways.
    

2.
Let me tell you about the disruptive breakthrough in advanced chip manufacturing technology using the example of Changdian Technology.
   

This year, Changdian Technology made a major decision to launch a full range of solutions under the registered trademark XDFOI in the international track of heterogeneous integration. This is based on the 2D packaging that Changdian Technology is currently mass-producing, and based on our ability to integrate multiple 5-nanometer SOCs and multiple high-bandwidth memories in MCM and SIP, which have already been mass-produced. Now, we are gradually moving towards 2.5D and 3D chip-oriented solutions, which are introduced one project at a time with customers, stacking more chips together at a high density, and combining chips with high-density wiring layers, including different forms, a series of combination circles facing the track of heterogeneous integration, and are actively accelerating.
   

We have accumulated a lot of experience this time. Changdian Technology has accumulated nearly 10 years of experience in mass production of fan-out technology. Combined with high-density SIP technology, we have promoted a series of product solutions including 2.5D chipled, 2D chipled, and 3d chipled for chiplets, and introduced them to customers. As I just mentioned, we have mass production projects and solutions for different products in 2022 and 2023. This has chipled high-density integration solutions for related applications that are very important in the market, such as high-performance computing, artificial intelligence, automotive electronics, medical, and communications.
   

When people talk about 2.5D and 3D, TSMC talks about the most advanced packaging, which is to use TSV and chip stacking for high-speed interconnection. Changdian Technology is different. This time, we launched a series that uses blind hole interconnection to form an intorposer to form high-speed interconnection between chips. Because TSV costs are very high, the key is that the yield rate has not yet met the industry's requirements, but intorposer is very effective in terms of cost and yield control. This is the know-how of Changdian Technology's accumulated fan-out high-density packaging to form our technology. Therefore, the technology launched can achieve multi-layer IDO wiring. At present, it can achieve a line width spacing of 2×2. In the next two years, it can achieve a high-density line width spacing of 1×1, 40 microns, and then a very narrow bump interconnection of 20 microns, multi-layer chip stacking, integrated high-bandwidth storage, and integrated passive components.
   

The red color is the IDO rewiring layer. We also make a wafer in the back end. What is the difference between it and the front-end wafer factory? Theirs makes circuits, while ours makes a wafer specifically for high-density interconnection. This wafer is combined with the front-end wafer and finally the high-density heterogeneous integrated chips are integrated together through superposition and interconnection. It can also be based on the chip size. If it is relatively small, a package can be used. If the chip is relatively large, exceeding 20×20, it can be combined with a high-density guided BGA packaging form to provide large and high-density chip solutions for high-performance computing.
   

I would like to say one more thing. Through high-density system-level packaging, SIP is also similar to Chipled. It is also a part of chipled, or chipled is also a part of SIP. All the chips currently made for wearables are put together in a SIP module. The chips that are already in mass production, including chips under development for 6G, high-density SIP chips for 5G millimeter waves made in 5G, and 3-layer SIP stacked double-sided sealing, are also worthy of everyone's study and attention. It is also another way for technology to break through in the post-Moore era.