Portable Dynamic Signal Analyzer Based on TMS320F2812

1 Introduction

In the field of electronic measurement, dynamic signal analyzers are called "RF multimeters" in the frequency domain, which shows their importance and wide application. Dynamic signal analysis is to convert time domain signals into frequency domain for processing, which generally requires the use of time window technology, such as fast Fourier transform (FFT), discrete Fourier transform (DFT), etc. If the sampling points are N, direct DFT operation requires N2 multiplication operations, which requires a lot of computing time. FFT operation can reduce the operation to (N/2)log2N multiplications, so FFT becomes the core algorithm of dynamic signal analysis.

Here, a design scheme of portable dynamic signal analyzer based on TMS320F2812 is proposed. It is based on digital signal processing, uses the powerful data processing capability of digital signal processor to analyze the collected signals, and optimizes the FFT algorithm of dynamic signals. It can realize the calculation and analysis of each frequency component and power spectrum and the measurement of distortion, and the analysis results are displayed on the liquid crystal display (LCD).

2 Principles of Dynamic Signal Analysis

Dynamic signal analysis methods include time domain analysis method and frequency domain analysis method. Among them, the frequency domain method is most suitable for dynamic signal analysis FFT algorithm. This system adopts FFT algorithm. Its essence is a fast algorithm of DFT. FFT algorithm decomposes long sequence DFT into the sum of short sequence DFT according to its symmetry and periodicity. N-point DFT is first decomposed into 2 N/2-point DFTs, and each N/2-point DFT is decomposed into N/4-point DFT. The number of points of the minimum transformation is the so-called "radix" of FFT. Therefore, the minimum transformation of DFT with radix 2 is 2-point DFT (or butterfly operation). In the N-point FFT with radix 2, let N=2, then it can be divided into M levels of operations in total, and there are (N/2)log2N butterfly operations in each level. Then N-point FFT has a total of (N/2)log2N butterfly operations, and one butterfly operation only requires one complex multiplication. For N-point FFT, (N/2)log2N complex multiplications and (N/2)log2N complex additions need to be calculated. Generally speaking, the computational complexity of FFT is much smaller than that of DFT. An N-point FFT requires (N/2)log2N multiplication operations, while an N-point DFT requires (N/2)log2N multiplication operations. Therefore, the computational complexity of an N-point DFT is approximately 2N/log2N times that of an FFT. To analyze the frequency components of a dynamic signal, first sample N points (N=2M) at a sampling frequency fs, and obtain its spectrum through fast Fourier transform.

According to the spectrum resolution F=fs/N, if the number of sampling points N is kept constant, to improve its resolution (F decreases), the sampling frequency must be reduced. The reduction of sampling frequency will cause the spectrum analysis range to decrease. If fs is kept constant, the number of sampling points N can be increased to improve the frequency resolution, because NT=Tp, T=fs-1, and N can only be increased by increasing the observation time Tp of the signal. Tp and N can be selected according to the conditions of .

3 System Hardware Circuit Design

The hardware structure of the portable dynamic signal analyzer is shown in Figure 1. The input signal to be detected is sent to the 12-bit A/D converter inside the TMS320F2812 DSP for sampling after the conditioning circuit with the operational amplifier LM358 as the core. The digital output signal is sent to the DSP core processing unit for FFT processing. After DSP operation processing, the calculation of each component frequency value and power value, the calculation of signal distortion and the detection of periodic signals are realized, and the analysis results are displayed on the screen LCD. The keyboard adopts keyboard query mode interrupt processing to realize the switching of various working modes and display interfaces.

3.1 Conditioning Circuit

When designing the conditioning circuit, the voltage amplitude of the sampled signal needs to be conditioned to the range that the A/D converter can receive and the high-frequency noise signal needs to be filtered out, so a cascade method is used. The first stage selects the high-precision integrated operational amplifier LM358 to form a voltage follower, which has an isolation effect; and the second stage amplifier circuit realizes the proportional amplification and low-pass filtering of the signal, as shown in Figure 2. In Figure 2, the operational amplifier LM358 constitutes a reverse proportional amplification circuit, Ui is the voltage signal isolated by the first stage voltage follower, R1 and R3 constitute a reverse proportional circuit, which proportionally reduces the input signal by 4.7 times, and C3 and R3 constitute an RC low-pass filter network. The circuit cutoff frequency f=1/2πR3C3=1/2π×1 kΩ×0.01 μF=15 923 Hz, which meets the design requirements (the signal frequency range is 0 to 10 000 Hz). Pin 7 and pin 4 are respectively connected to a 0.1μF ceramic capacitor to filter out high frequencies. In order to reduce the offset current, pin 3 is connected to R2 (whose resistance is approximately the parallel resistance of R1 and R3); the output signal U0 is sent to the third-stage adding circuit. The third-stage adding circuit can raise the signal above 0 V to meet the A/D conversion requirements (the system uses the internal A/D converter of TMS320F2812). After the conditioning is completed, it is sent to the DSP for digital signal processing.

3.2 System Control Unit

The system control unit uses the 32-bit fixed-point digital signal processor TMS320F2812. The device uses high-performance static CMOS technology with a main frequency of 150 MHz, which shortens the instruction cycle by 6.67 ns, thereby improving the real-time control capability of the controller. Its high-performance 32-bit CPU and single-cycle 32x32 multiplication and accumulation operation characteristics can complete 64-bit data processing and achieve high-precision processing tasks. It has efficient code conversion functions (supports C/C++ and assembly) and is compatible with TMS320F24x/LF240x program codes. The on-chip memory resources include: 128 K×16-bit Flash, 128 K×16-bit ROM, 18 K×16-bit SARAM, and 1 K×16-bit one-time programmable memory OTP. The on-chip Flash/ROM has programmable encryption features, which is convenient for on-site software upgrades. TMS320F2812 has a 128-bit protection password to prevent illegal users from viewing the contents of Flash/OTP/L0/L1, accessing peripherals and loading certain illegal software through the JTAG emulation interface, ensuring the security of relevant data. The A/D converter has 16 channels and can be configured into two independent 8-channel modules to facilitate the service of event manager A and event manager B. These two independent 8-channel modules can be cascaded into a 16-channel module. Although the A/D converter has abundant input channels and two sequencers, it only has one converter. The two 8-channel modules automatically sequence the conversion, and any 8-channel module is selected through a multiplexer. In cascade mode, the automatic sequencer acts as a 16-channel sequencer. Once each sequencer completes the conversion, it stores the value of the selected channel in its respective ADCRESULT register. Automatic sequencing allows multiple conversions of the same channel, allowing users to use oversampling algorithms, which will improve the accuracy of the results compared to traditional single-shot conversions.

In order to obtain the specified A/D converter accuracy, the correct circuit board layout must be used. For the best effect, the ADCINxx pin should be as far away from the digital signal line as possible to eliminate the coupling between the switching noise in the digital circuit and the A/D converter input to the greatest extent; at the same time, the power pin of the A/D module and the digital power supply must be properly isolated.

3.3 Display module LCD

CMl2864-10 is a graphic dot matrix LCD display, which is mainly composed of row driver/column driver and 128x64 full dot matrix LCD display, which can display graphics and 8×4 Chinese characters (16×16 dot matrix). The interface circuit of LCD and DSP is shown in Figure 3. Since TMS320F2812DSP is a low-power design, all digital inputs are compatible with TTL, all outputs are 3.3 V CMOS level, and cannot receive 5 V input. The LCD interface of the display module is 5 V input and output, so the level converter SN74ALVCl64245 is also required in practical applications.

4 System Software Design

The system software includes the main program, capture interrupt service subroutine, T1 periodic interrupt service subroutine, A/D conversion interrupt service subroutine, FFT operation subroutine and LCD display subroutine. The main program mainly completes the system initialization, including CPU, PIE register, PIE interrupt vector table, LCD screen, A/D converter initialization, etc., as well as querying the working mode setting. According to different working modes, the corresponding service subroutine is entered. The main program flow is shown in Figure 4.

Set two breakpoints. When the program reaches the breakpoints, observe the received data and display the image. When the program reaches the first breakpoint, the A/D sampling is completed. At this time, you can set the image to observe the result of A/D sampling (i.e. display the Ad_data1 array); when the program reaches the second breakpoint, the FFT transformation is completed. You can set the image to observe the result after FFT transformation without modulo (i.e. display the ipcb array); continue to run the program. After stopping, the program will stop at the loop statement. You can also set the image to observe the result after modulo, i.e. display the mod array. Figure 5 shows the image display of the 1024-point Ad_data1 array, ipcb array, and mod array from top to bottom. The horizontal axis is the number of sampling points. The vertical axis is the signal amplitude.

5 Conclusion

For spectrum analysis, the design is based on TMS320F2812 DSP dynamic signal analyzer. On this basis, a series of data processing measures are used to realize the FFT transformation of real numbers. For dynamic signal analysis, the sampling rate of A/D determines that the frequency of the processed signal is below 20 kHz. Before analyzing the spectrum, the signal frequency range needs to be estimated, and then the sampling rate is adjusted to ensure that 1 024 points can sample more than one cycle. At the same time, Shannon's sampling theorem must be met. The system is controlled by TMS320F2812DSP, with fewer peripheral circuits, stable system, strong functions, easy operation, and low cost. It has wide application value.