Design and simulation of reconfigurable CNC system based on DSP+CPLD

1. Introduction

With the rapid development of computer technology, industrially developed countries have invested heavily in the research and development of modern manufacturing technology and proposed a new manufacturing model. One of its core ideas is flexible manufacturing, and the manufacturing system can be dynamically adjusted as the processing conditions change. At present, various types of MCUs are developing rapidly. They are not only fast in operation, cheap, and diverse, but also different MCUs integrate dedicated control circuits on their chips for different applications, which meets different application requirements and improves the safety and stability of the circuit. Based on the above analysis and demonstration, this paper designs a reconfigurable CNC system based on DSP+CPLD field programmable gate array devices.

2. Hardware Design

This motion control card is a motion control card with PC as the host, and DSP is selected as the core microprocessor. The card integrates encoder signal acquisition and processing circuit, D/A output circuit, expansion memory circuit and PC-DSP communication circuit. PC transmits the roughly processed data to the motion control system through the DSP-PC communication interface. DSP calculates the error value with the given position by analyzing the result of the photoelectric encoder feedback signal processing circuit, and then obtains the position control amount through the software position regulator, calculates the motion speed control amount, and the generated output signal is converted into analog voltage by D/A to send it to the servo amplifier, and the closed-loop control of the position is realized by controlling the servo motor. The structural block diagram of the system is shown in Figure 1.

The 16-bit fixed-point DSPTMS320LF2407A from TI of the United States is selected as the core processor of this motion controller. The address decoding, timing logic, and encoder signal processing circuits are completed using CPLD. The PCI interface chip is used to realize the communication between the dual-port RAM and the PC. The dual-port RAM is used to store and buffer the communication data between the DSP and the PC. The SRAM is used to store the programs and data when the motion controller is running.

(1).DSP external interrupt interface processing

For CNC machine tools, due to the limitations of various aspects such as the working stroke, when it exceeds the control range, limit interrupts and encoder INDEX signal interrupts are introduced. Each control axis has two limit switches in the positive and negative directions, generating two limit signals. There are 8 limit signals for 4 axes: LIMA+, LIMA-, LIMB+, LIMB-, LIMC+, LIMC-, LIMD+, LIMD-, where "+" indicates positive limit and "-" indicates negative limit. These signals are connected to the interrupt pin XINT1 of DSP after being ANDed by CPLD, and these signals are connected to the I/O port of DSP through the optical coupling circuit. When moving to the limit switch, the external interrupt signal XINT1 of DSP will be triggered, and then DSP can determine which limit switch exceeds the working range according to I/O. The 8 limit switches are connected to the I/O port of DSP respectively, and these multiplexed pins are in I/O function by setting MCRA (address: 7090H) and MCRB (address: 7092H) to zero. The state of the limit input signal can be read from the corresponding data bits of the registers PADATDIR (address: 7098H) and PBDATDIR (address: 709AH), and the corresponding data direction bits are set to zero to make these I/O pins work in the "input" state. The INDEX signal processing of the encoder is similar to the above. Each axis can generate an INDEX signal, and 4 axes have 4 INDEX signals. These 4 signals generate an interrupt signal through the logic AND gate, which is connected to XINT2 and the DSP's I/O port for the DSP to read when the interrupt occurs.

(2) Design of four-axis encoder signal processing circuit

The four-axis encoder signal processing circuit processes two sets of square wave signals with a phase difference of 90o output by the photoelectric encoder to obtain the actual position of the actuator. Its output is a 16-bit digital quantity, which is fed back to the central processor. The encoder signal processing circuit includes several functional modules such as filtering, frequency multiplication, and counting. The traditional four-axis encoder signal processing circuit is designed with discrete components, which has poor reliability and anti-interference ability. CPLD is used to design a single-chip parallel four-axis encoder signal processing circuit.

It has good real-time performance, small hardware size, high working efficiency, and improves the integration of the system. Compared with discrete components, the single-chip parallel four-axis encoding signal processing circuit is integrated on a single chip. On the one hand, the parameter characteristics of the gate circuit and trigger in the single chip are completely consistent, and the pulse period of the pulse signal can be kept consistent at the same speed. On the other hand, the circuit is made in a single chip, and the anti-interference performance is also greatly improved compared with the circuit composed of separate devices, which enhances the flexibility, versatility and reliability of the system. This paper designs a four-axis servo system, so there are eight channels and four groups of square wave signals, with a phase difference of 90o between phase A and phase B. CLR, CLK, and WE are output clear, system clock, and output enable, respectively. SEL* is the output selection signal, which selects a group of signal processing results from X, Y, Z, and A as the output signal and sends it to the data bus in time-sharing.

Design of filter module

The encoder disk is a stable square wave signal in theory, but in actual operation, there is often pulsation interference. The function of the filter module is to filter out these pulsation interferences, reduce the possibility of system malfunction, and improve system reliability. The following VHDL program delays four CLK pulses for the A and B two-phase square wave signals at the same time. The input signal with a pulse width less than three CLK pulse cycles is filtered out. The simulation results are shown in the figure: