Chip-Package Co-Design Methodology Optimizes SoC Design

As process nodes and die sizes continue to shrink, the number of consumer electronic products using flip-chip packaged IC devices is increasing. However, flip-chip packaging manufacturing rules have not kept pace with process technology development.

Therefore, a more accurate and efficient I/O interface design method is needed, especially for flip-chip designs. This integrated chip-package co-design method should allow early feasibility studies and optimize the package and chip interface design while meeting the strict constraints required by the chip and package.

Currently, most flip chip design companies use an in-house approach to flip chip planning. This approach primarily uses spreadsheets to capture and store design inputs and constraints. Companies develop their own scripts to process the data in the spreadsheets and generate instructions to guide the design implementation. This approach usually starts with a simple system and then gradually develops into a complex set of formats and scripts as the design complexity increases.

This approach has many disadvantages. First, such systems are expensive to maintain and reduce designer productivity. Second, spreadsheets are very limited in how they describe designs. Third, scripts lack the comprehensive capabilities to perform what-if analyses or optimize designs for cost, performance, and reliability. Fourth, spreadsheet- and script-based systems cannot accurately predict the final implementation of a design.

Collaborative design environment

As die sizes continue to shrink and I/O counts and speeds continue to increase, the interface between chip and package quickly becomes the most constrained part of the design. Being able to design both the package and chip in a timely and simultaneous manner with high quality and low cost can make the difference between a successful product and a mediocre or failed chip.

Therefore, an integrated chip-package co-design system is needed, which uses the industry-standard database OpenAccess and can interface with third-party packaging and interface implementation tools. This integrated design environment allows designers to view and manipulate chip and package data in a single database. Because the design database contains complete package and chip implementation data, this database can be used by both chip and package design teams.

The Tcl interface allows users to develop Tcl scripts to detect design data, generate data reports, and automate the design process. Data exchange can also be achieved between the collaborative design environment and third-party chip and package implementation tools by using databases or standard interfaces such as LEF/DEF.

An efficient package and chip co-design solution must have the ability to quickly prototype, because package decisions need to be made early in the design cycle, when the design netlist and/or physical library are not yet ready. It is also important to predict the accuracy of the final implementation. Without sufficient accuracy, design decisions made during the prototyping or planning stages may lead to implementation difficulties, which can seriously affect the time to tape out.

Conservative planning may increase packaging costs unnecessarily. Co-design systems need to allow users to develop multiple scenarios to allow designers to test different packaging solutions. With this capability, users can prototype with different substrate stacking methods and find the cheapest packaging solution through feasibility checks.

Any design parameter changes are incremental, and the design can be automatically updated with the modified settings. For example, if the user wants to experiment with a substrate with fewer layers, or a smaller BGA, or a different ratio of I/O pad cells, the user can import/generate a new substrate stack-up scheme, or generate another BGA, or build a new set of I/O cell prototypes in just a few minutes. Different design solutions can be saved as independent databases for comparison and design review. Each design can also be evaluated in terms of feasibility and cost.

Any planning tool needs to correlate well with the final implementation. A plan is only perfect if it can be successfully implemented. When using traditional methods, package layout designers must manually confirm the routability of the package. Doing so will extend the project time and increase the number of packages used for evaluation.

An integrated chip-package co-design environment should include an automated package feasibility router for rapid and accurate evaluation of many packages. This package feasibility analysis is key to reducing engineering iterations between design teams and package suppliers.

Since most package modifications and verification can be done in the same package-chip co-design environment, detailed package layout is only required for final layout implementation and verification.

Most flip chip designs today rely on well-known bump patterns. This "one size fits all" solution can lead to significant over-design and unnecessary packaging cost.

The integrated flip chip package co-design solution provides a complete set of creation functions from automatic to fully customized. It can automatically synthesize the bump-cover macro that can be routed in the selected package and meet the SPG (signal to power and ground) constraints, and can also import customized bump-cover macros from file formats.

In addition, a robust layout editor allows users to intuitively create and edit bump overlay macros in a GUI. With a library of bump overlay macros, the system can select the best macro for the design, resulting in a smaller die area, fewer package routing layers, and better power and ground distribution.

The comprehensive approach used in this system determines the optimal bump layout, resulting in the most cost-effective solution and meeting the most stringent constraints.

One of the most important advantages of an integrated chip-package co-design planning environment is that it can consider constraints from both the package and chip perspectives. When there are conflicts in constraints, the tool needs to make intelligent arbitration.

In the design example shown in Figure 1, the die is being migrated to a new technology and the existing package interface needs to be reused as much as possible. In this case, the package ball assignments can be obtained from a spreadsheet, where the ball assignments on the east and west sides of the package are fixed and their interfaces to the PCB will be reused.

Figure 1: Example of bare die migration with fixed package and chip constraints [page]

Due to timing constraints, the north side of the chip has a fixed interface, so the package balls on the north side need to be reallocated to match the fixed chip interface.

On the south side of the chip, the designer is free to optimize the package ball assignments and chip I/O pad layout. Areas highlighted in white have fixed chip or package constraints.

The challenge here is to automatically design the layout of the chip I/O pads, the bumps of the flip chip, and the package balls, while satisfying the fixed constraints in the chip and package. Without an integrated co-design tool, this work would take weeks of manual design time. Any subsequent changes on the chip or package side may require several days of data synchronization.

The integrated chip-package co-design system can handle both package and chip constraints. Data synchronization between chip and package can be automatically completed by the constraint-driven I/O placement, bump allocation and package ball allocation engine.

Figure 2(a) shows the design status after the initial chip I/O layout without package constraints. Due to the fixed package balls, the package is not routable.

Figure 2(b) shows the result after package-driven I/O placement on the east and west sides, where the I/O cells are replaced and the bumps are reallocated to ensure routability to the fixed package balls.

Figure 2(c) shows the result after completing the chip-dominated package ball assignment on the north side of the chip, where the package balls are reallocated to ensure the routability to the fixed I/O interfaces on the chip.

Figure 2(d) shows the result after the design is completed, where the tool has automatically completed the optimization of chip I/O layout, bump allocation, and south-side package ball allocation. Constrained automation can complete this task in minutes or hours, while the corresponding manual operation would take days or even weeks.

Figure 2: Meeting package and chip constraints using an integrated chip-package co-design system.

Design Modifications

Design modifications can occur early in the design planning phase or as late as before tapeout. Completing modifications in a traditional environment is painful because it requires a lot of manual work. In addition, there is a risk of data inconsistency between the chip and the package.

An integrated chip-package co-design solution using a single database can automatically handle ECOs (engineering change orders). If the changes can be passed down the design hierarchy without violating the hardware design constraints, then the package changes are acceptable. The package and chip layout are automatically updated.

Likewise, chip design changes can be propagated upward to the package level if feasible. When conflicts exist between chip and package constraints, the tool provides the user with a way to arbitrate between the chip and package. Most importantly, because ECOs are handled in a single database, it guarantees data consistency between chip and package, and built-in data checkers ensure that the design has pure LVS (layout to schematic).

Conclusion

Today, tapeout of a large SoC design requires advanced floorplanning tools. Flip-chip planning is evolving along similar lines. SoC design requires more accurate and efficient I/O interface design methods, especially for flip-chip designs. This integrated chip-package co-design approach should allow for early feasibility studies and optimize the package and chip interface design while meeting the tight constraints required for both chip and package. Chip co-design solutions are becoming a unique factor in reducing design costs and meeting time-to-market requirements.