Take you to understand TI's DSP entry chip TMS320F28335

　　As an electronic hardware engineer, how can you not understand DSP? Or some of us don't know much about DSP. Today, let us introduce to you an entry-level DSP chip, TMS320F28335 from TI. I believe that after reading this series of content, everyone will have a preliminary understanding of DSP.

　    TMS320F28335 Introduction:

　　TMS320F28335 adopts 176-pin LQFP quad package, and its functional structure can be found in the references. Its main performance is as follows:

　　High-performance static CMOS technology, instruction cycle of 6.67 ns, main frequency of 150 MHz;

　　High-performance 32-bit CPU, single-precision floating-point unit (FPU), Harvard pipeline structure, fast interrupt response, unified memory management mode, and can implement complex mathematical algorithms in C/C++ language;

　　6-channel DMA controller;

　　On-chip 256 Kx16 Flash memory, 34 Kx16 SARAM memory, 1 Kx16 OTPROM and 8 Kx16 Boot ROM. Flash, OTPROM and 16 Kx16 SARAM are all password protected.

　　The control clock system has an on-chip oscillator, a watchdog module, supports dynamic PLL adjustment, and an internal programmable phase-locked loop. The input clock frequency of the CPU can be changed by setting the value of the corresponding register through software;

　　8 external interrupts, compared to the TMS320F281X series DSP, there is no dedicated interrupt pin. GPI00~GPI063 are connected to this interrupt. GPI00-GPI031 are connected to XINT1, XINT2 and XNMI external interrupts, GPI032~GPI063 are connected to XINT3-XINT7 external interrupts;

　　A peripheral interrupt expansion controller (PIE) that supports 58 peripheral interrupts and manages interrupt requests caused by on-chip peripherals and external pins;

　　Enhanced peripheral modules: 18 PWM outputs, including 6 high-resolution pulse width modulation modules (HRPWM), 6 event capture inputs, and 2-channel quadrature modulation modules (QEP);

　　Three 32-bit timers, Timer 0 and Timer 1 are used as general timers, Timer 0 is connected to the PIE module, Timer 1 is connected to interrupt INT13; Timer 2 is used for the on-chip real-time system of DSP/BIOS, connected to interrupt INT14. If the system does not use DSP/BIOS, Timer 2 can be used as a general timer;

　　The serial peripherals include a 2-channel CAN module, a 3-channel SCI module, 2 McBSP (multi-channel buffered serial interface) modules, 1 SPI module, and 1 I2C master-slave compatible serial bus interface module;

　　The 12-bit A/D converter has 16 conversion channels, 2 sample-and-hold devices, internal and external reference voltages, a conversion speed of 80 ns, and supports multi-channel conversion.

　　88 programmable multiplexed GPIO pins;

　　Low power mode;

　　1.9 V core, 3.3 V I/O power supply;

　　The on-chip scan emulation interface (JTAG) complies with the IEEE 1149.1 standard; the memory mapping of the TMS320F28335 should pay attention to the following points:

　　On-chip peripheral register blocks 0 to 3 can only be used as data storage areas, and users cannot write programs in this storage area.

　　The OTP ROM area (0x38 0000~0x38 03FF) is a read-only space that stores the calibration program of the A/D converter. Users cannot write programs to this space.

　　Even if the eCAN module is not applied, the clock module should be enabled and the RAM space allocated for eCAN should be used as general RAM.

　　If the security code is set, the memory area 0x33FF80~0x33FFF5 must all be written with data 0x0000 and cannot be used to store programs or data. On the contrary, 0x33FF80~0x33FEF can store data or programs, while 0x33FFF0~0x33FFF5 can only store data.

　　Simulation tools and development environment:

　　The TMS320F28335 development tools include: standard optimized C/C++ compiler/assembler/connector, CCS integrated development environment, evaluation board and XDS510 simulator. CCS is a user-friendly, fully functional integrated development platform with editing, assembly, compilation, software and hardware simulation debugging functions.

　　TMS320F28335 ADC:

　　The TMS320F28335 has a 16-channel, 12-bit analog-to-digital converter ADC. It can be configured as two independent 8-channel input modes, or it can be set to a 16-channel cascade input mode by configuring AdcRegs.ADCTRL1.bit.SEQ_CASC=1. The input method can be set to sequential acquisition by configuring AdcRegs.ADCTRL1.bit.ACQ_PS=1. That is, starting from the low channel and ending at the high channel. It is worth noting that the input voltage range of the on-chip ADC is 0--3V. Once it exceeds 3V, the on-chip ADC module will be burned. The DATASHEET on TI introduces that the accuracy of its ADC can reach 12 bits, but it cannot be achieved in reality. After testing, we estimate that it would be good to reach 11 bits at best. Let's briefly introduce the principle of the ADC module. Its digital value is calculated by the following company, where 3 in the formula is the on-chip reference voltage Digital Value=4096*(Input Analog Voltage-ADCLO)/3; (when 0 V < input < 3 V). ADC can be divided into two modules, SEQ1 and SEQ2, where SEQ1 includes ADCIN00--ADCIN07; SEQ2 includes ADCIN08--ADCIN15. SEQ1 module can be started by software, PWM, external interrupt pin, while SEQ2 cannot be started by external interrupt pin. In addition, ADC can exchange data with DMA.　　Introduction to the clock of TMS320F28335:

　　The TMS320F28335 has an on-chip clock module based on a PLL circuit. There are two ways to provide clocks for the CPU and peripherals: one is to use an external clock source, connect it to the X1 pin or the XCLKIN pin, and ground X2; the other is to use an oscillator to generate the clock, and connect a circuit consisting of a 30MHz crystal and two 20PF capacitors to the X1 and X2 pins respectively, and the XCLKIN pin is grounded. We often use the second method to generate the clock. This clock will be multiplied by an internal PLL phase-locked loop circuit. Since the maximum operating frequency of the F28335 is 150M, the maximum multiplication value is 5. The multiplication value is determined by the lower four bits of the PLLCR and the 7th and 8th bits of the PLLSTS. The detailed multiplication value can be referred to the TMS320F28335 Datasheet. The following is the clock setting of the F28335:

　　void InitPll(Uint16 val, Uint16 divsel)

　　{

　　// Make sure the PLL is not running in limp mode

　　if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)

　　{

　　// Missing external clock has been detected

　　// Replace this line with a call to an appropriate

　　// SystemShutdown(); function.

　　asm("ESTOP0");

　　}

　　// DIVSEL MUST be 0 before PLLCR can be changed from

　　// 0x0000. It is set to 0 by an external reset XRSn

　　// This puts us in 1/4

　　if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)

　　{

　　EALLOW;

　　SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;

　　EDIS;

　　}

　　// Change the PLLCR

　　if (SysCtrlRegs.PLLCR.bit.DIV != val)

　　{

　　EALLOW;

　　// Before setting PLLCR turn off missing clock detect logic

　　SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;

　　SysCtrlRegs.PLLCR.bit.DIV = val;

　　EDIS;

　　// Optional: Wait for PLL to lock.

　　// During this time the CPU will switch to OSCCLK/2 until

　　// the PLL is stable. Once the PLL is stable the CPU will

　　// switch to the new PLL value.

　　//

　　// This time-to-lock is monitored by a PLL lock counter.

　　//

　　// Code is not required to sit and wait for the PLL to lock.

　　// However, if the code does anything that is timing critical,

　　// and requires the correct clock be locked, then it is best to

　　// wait until this switching has completed.

　　// Wait for the PLL lock bit to be set.

　　// The watchdog should be disabled before this loop, or fed within

　　// the loop via ServiceDog().

　　// Uncomment to disable the watchdog

　　DisableDog();

　　while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)

　　{

　　// Uncomment to service the watchdog

　　//ServiceDog();

　　}

　　EALLOW;

　　SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;

　　EDIS;

　　}

　　// If switching to 1/2

　　if ((divsel == 1) || (divsel == 2))

　　{

　　EALLOW;

　　SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;

　　EDIS;

　　}

　　// If switching to 1/1

　　// * First go to 1/2 and let the power settle

　　// The time required will depend on the system, this is only an example

　　// * Then switch to 1/1

　　if (divsel == 3)

　　{

　　EALLOW;

　　SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;

　　DELAY_US(50L);

　　SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;

　　EDIS;

　　}

　　} T MS320F28335 external interrupt summary:

　　Here we need to be very clear about the interrupt system of DSP. C28XX has a total of 16 interrupt sources, including 2 non-maskable interrupts RESET and NMI, and timer 1 and timer 2 use interrupts 13 and 14 respectively. In this way, there are 12 interrupts directly connected to the peripheral interrupt expansion module PIE. To put it simply, PIE is connected to the 12 interrupt lines of the 28335 core through 12 wires. On the other side of PIE, there are 12*8 wires connected to peripherals, such as AD, SPI, EXINT, etc. In this way, PIE manages a total of 12*8=96 external interrupts. These 12 groups of large interrupts are controlled by the interrupt register IER of the 28335 core, that is, IER determines which group of large interrupts each interrupt belongs to (such as IER |= M_INT12; means that we want to use the interrupt of the 12th group, but the CPU does not know what interrupt in the 12th group needs to be determined by PIEIER). Next, the lower 8 bits of the register PIEIER in the PIE module determine which interrupt this interrupt belongs to in this group. These configurations must be told to the CPU (it is not difficult to imagine that there are 12 PIEIERs in total, from PIEIER1 to PIEIER12). In addition, the PIE module also has an interrupt flag register PIEIFR. Similarly, its lower 8 bits are the 8 flag bits from the external interrupt. Similarly, the IFR register of the CPU is the flag register of the interrupt group. From this point of view, all interrupt registers of the CPU control 12 groups of interrupts, and all interrupt registers of the PIE control 8 interrupts in each group. In addition, whichever external interrupt we use, there is also a corresponding external interrupt register. It should be noted that the flag of the external interrupt must be cleared by software. The interrupt flag registers of PIE and CPU are cleared by hardware.

　　EALLOW; // This is needed to write to EALLOW protected registers

　　PieVectTable.XINT2 = &ISRExint; //Tell the interrupt entry address

　　EDIS; // This is needed to disable write to EALLOW protected registers

　　PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block to enable PIE

　　PieCtrlRegs.PIEIER1.bit.INTx5 = 1; // Enable interrupt 5 in the first group

　　IER |= M_INT1; // Enable CPU first group interrupt

　　EINT; // Enable Global interrupt INTM

　　ERTM; // Enable Global realtime interrupt DBGM

　　That is to say, each interrupt in the 12 groups must complete the same configuration as above, and the rest is to configure its own interrupt. As we mentioned EXINT, that is, when there is a low level outside, we enter

　　Interrupt, complete our program. Here we need to introduce that the DSP's GPIO port can be configured as an external interrupt port, and the configuration method is as follows:

　　GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 0; //Select them as GPIO ports

　　GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 0;

　　GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 0;

　　GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 0;

　　GpioCtrlRegs.GPBDIR.bit.GPIO54 = 0; //Select them as input ports

　　GpioCtrlRegs.GPBDIR.bit.GPIO55 = 0;

　　GpioCtrlRegs.GPBDIR.bit.GPIO56 = 0;

　　GpioCtrlRegs.GPBDIR.bit.GPIO57 = 0;

　　GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 0; //GPIO clock is the same as system clock and supports GPIO

　　GpioCtrlRegs.GPBQSEL2.bit.GPIO55= 0;

　　GpioCtrlRegs.GPBQSEL2.bit.GPIO56= 0;

　　GpioCtrlRegs.GPBQSEL2.bit.GPIO57= 0;

　　GpioIntRegs.GPIOXINT3SEL.bit.GPIOSEL = 54; //Interrupt 3 selects GPIO

　　GpioIntRegs.GPIOXINT4SEL.bit.GPIOSEL = 55;

　　GpioIntRegs.GPIOXINT5SEL.bit.GPIOSEL = 56;

　　GpioIntRegs.GPIOXINT6SEL.bit.GPIOSEL = 57;

　　XIntruptRegs.XINT3CR.bit.POLARITY = 0; //Trigger mode is falling edge trigger

　　XIntruptRegs.XINT4CR.bit.POLARITY= 0;

　　XIntruptRegs.XINT5CR.bit.POLARITY= 0;

　　XIntruptRegs.XINT6CR.bit.POLARITY= 0;

　　XIntruptRegs.XINT3CR.bit.ENABLE = 1; // Enable interrupt

　　XIntruptRegs.XINT4CR.bit.ENABLE = 1;

　　XIntruptRegs.XINT5CR.bit.ENABLE = 1;

　　XIntruptRegs.XINT6CR.bit.ENABLE = 1;

　　One thing to note is that external interrupts 1 and 2 can only be configured for GPIO0-GPIO31; external interrupts 3 and 4, 5, 6, and 7 can only be configured for GPIO32-GPIO63.

　　Design and implementation of signal processing board based on TMS320F28335

　　Hardware system design

　　1.1 Overview of the Solution

　　The main function of the system is that the DSC samples 12 analog signals simultaneously through the ADC sampling chip. After the data is processed in the DSC, it is uploaded to the host computer through the asynchronous serial transceiver. At the same time, the host computer can also send pre-defined commands to the DSC through the asynchronous transceiver to control the working mode and status of the signal processing board.

　　According to the functional requirements, the entire hardware circuit can be divided into three parts: power module, digital part and analog part. Its functional structure block diagram is shown in Figure 1.

　　1.2 Power module design

　　The external input voltage of the entire processing board is 5 V and ±12 V, and different voltage amplitudes are provided for the analog and digital parts through the corresponding voltage conversion chips. For the digital part, the power module needs to provide 1.9 V core voltage for the DSC, and 3.3 V peripheral voltage for the DSC periphery and other chips. This system uses the LT1963AES8 integrated chip to provide 1.9 V, and the LT1963AEST-3.3 integrated chip to provide 3.3 V. For the analog part, the system requires the signal amplitude range of the input ADC to be within ±12V, so the system uses LT1086IT-12 and LT1175IT to convert the input ±15V voltage into ±12V.

　　1.3 Digital Circuit Design

　　The digital circuit is mainly an application circuit centered on DSC. This part mainly processes and stores the data transmitted by ADC, and completes the communication and data transmission between DSC and the host computer. As can be seen from Figure 1, it includes the following parts: peripheral SRAM expansion, EEPROM expansion circuit, SCI host computer communication interface circuit.

　　1.3.1 Peripheral SRAM expansion

　　Considering the limited RAM resources in the TMS320F28335 chip, and the fact that the program space and data space RAM are only 34 kB and 16-bit data width, it is necessary to expand the RAM in the chip to meet the running of a large number of programs. This system uses the Cypress CY7C1011CV33-12ZSXE integrated chip and uses the XINTF interface provided by the TMS320F28335 to complete the expansion of the off-chip RAM.

　　XINTF is a non-multiplexed asynchronous bus provided by TMS320F28335, which is used to expand external asynchronous devices. XINTF can map peripherals to three fixed memory mapping areas. When external resources are attached to a certain area, a chip select signal of XINTF is required to select the external resources.

　　CY7C1011CV33-12ZSXE is a CMOS static RAM memory with a capacity of 64 kB and a data width of 16 bits. Figure 2 is a connection diagram of the peripheral SRAM expansion circuit.

　　As shown in Figure 2, this system uses ZONE7 as the peripheral expansion of RAM. DSC sends a chip select signal to the off-chip SRAM through its XZCS7 pin. The WE signal is used to control the DSC to read and write the off-chip SRAM. When the XWEo pin of the DSC is low, the DSC reads and writes the off-chip RAM; when XWEo is high and the XRD pin of the DSC is low, it is a read operation.

　　1.3.2 EEPROM expansion

　　Considering that after the system is powered on, the status of some devices needs to be initialized, and these initialized data need to be constantly changed when the device is running. Therefore, during the operation of the device, the data is saved in real time so that the data still exists after the device is powered off. This system uses the SPI interface of TMS320F28335 to expand an EEPROM to save the initialization data obtained in real time when the device is running. This system uses the AT25160 integrated chip of Atmel. The capacity of the chip is 2 kB, and its width is 8-bit data width. The module circuit is shown in Figure 3.

　　As shown in Figure 3, the DSC selects the EEPROM by sending a chip select signal through the SPISTEA pin, and sends the SPI transmission clock through the SPICLKA pin, while the writing and reading of data are completed through the SPIS-IMOA and SPISOMIA pins respectively. The HOLD pin in the EEPROM is used to suspend serial data transmission with the host device, and the WP pin is used to write-protect the EEPROM. If it is low, the host cannot write data to it. The system inputs a high level to the two pins to ensure that the EEPROM can continue to read and write without interruption.

　　1.3.3 SCI host computer communication interface

　　In order to realize asynchronous communication and data transmission between the host computer and DSC, this system uses the SCI interface provided by TMS320F28335 to meet the required requirements. SCI is a 2-wire asynchronous serial port, commonly known as UART. Its data transmission and reception supports full-duplex communication, and the internal transmission and reception have a 16-level FIFO to cache data. In order to ensure data reliability, SCI provides parity check, data overflow detection and other operations. The level of the SCI interface output signal is LV-TTL electrical standard, which is driven by the RS232 transceiver converter to obtain the RS232 electrical standard signal for the host computer to receive.

　　1.4 Analog Circuit Design

　　The analog circuit is mainly an application circuit centered on ADC. It mainly realizes the processing and collection of analog signals. The core part is AD conversion.

　　The AD conversion part mainly completes the conversion of analog signals to digital signals through digital sampling. The ADC chip selected in this system is the AD7656 from Analog Electric Company of the United States. The analog-to-digital conversion chip AD7656 is a highly integrated, 6-channel, 6-bit successive approximation (SAR) ADC with a built-in 2.5 V reference voltage and reference buffer. The power consumption of this device is 60% lower than that of the closest similar bipolar ADC. The accuracy of AD7656 at a sampling rate of 250 kb·s-1 per channel is twice that of similar products. The analog voltage range can be selected by pins and software: 10 V or 5 V; the analog power supply voltage range is 4.75 to 5.25 V, so the wide range of operating voltage allows it to be directly connected to the DSC without other measures such as level conversion; parallel and serial interfaces are provided. It can work at -40 to 85°C. The standard mode is powered by 5 V, and the power consumption is 140 mW at 250 kb·s-1, and only 100 μW in standby mode. The AD7656 manufactured based on iCOMS technology can meet the industrial field's high requirements for resolution, multi-channel, conversion rate and power consumption.

　　AD7656 supports parallel and serial data transmission with DSC, and controls the transmission mode of the sampled digital signal by selecting the high and low levels of the SER/PAR SEL pin. When it is high, the serial transmission mode is used, otherwise the parallel transmission mode is used. This system uses the parallel transmission mode. In the specific conversion process, the 6 sampling channels inside each AD7656 can be divided into 3 groups, A, B, and C, each of which contains 2 channels. The 3 groups of channels can be sampled simultaneously or separately, and the two channels in each group are sampled simultaneously. The pins CONVSTA, CONVSTB, and CONVSTC are used to control the A, B, and C sampling channels respectively. When a rising edge level reaches any pin, the 2 channels of analog-to-digital conversion corresponding to the pin are started and the analog-to-digital conversion begins. When the three pins are connected, 3 groups of sampling channels, that is, all 6 sampling channels are sampled simultaneously. The system selects 3 groups of channels to sample simultaneously.

　　When DSC is connected to multiple ADCs, the ADC selection needs to be performed through the CS chip select pin. When sampling starts, the BUSY pin will change from low level to high level. During the entire sampling process, BUSY remains at a high level. When sampling is completed, BUSY changes from high level to low level, and the DSC can start reading data. This system uses this pin as the input pin of the DSC external interrupt source. When the level on BUSY changes from high to low, the DSC is notified to generate an interrupt to read data.

　　This system uses two AD7656 chips to complete 12-channel data sampling. The ADC device is mapped to the DSC through the XINTF ZONE6 of the DSC for data transmission. The connection between the two ADCs and the DSC is achieved through address decoding and logic control. The specific structure is shown in Figure 4.

　　The lower left corner of Figure 4 is the logic part, and the ADC is selected through the address lines BA17 and BA18 of the DSC. It can be obtained that the address mapping of ADC0 and ADC1 in the DSC is 0x180000 and 0x1400 00. The external input clock of 40 kHz is used as the sampling frequency of the ADC. The two ADCs correspond to the same interrupt of the DSC. When any ADC completes sampling, it will cause an interrupt of the DSC, so as to read the sampled data.

　　2. System software design

　　As mentioned above, the entire signal processing board has a total of 12 analog signal paths, and 12 analog signals are received through sensors. Two AD7656s convert the 12 analog signals into digital signals and transmit them to TMS320F28335. After the collected data are processed accordingly in TMS320F28335, they are transmitted to the host computer through SCI. At the same time, the data that needs to be saved is saved to EEPROM through the SPI interface. The entire collection and communication process is controlled by the host computer sending relevant commands. The program flow is shown in Figure 5.

　　In the main function, the program first completes the initialization of the corresponding module, sets the CPU running clock, selects the working mode of each module, and then reads the device initialization data in the EEPROM, and then enters the waiting state. At this time, the CPU waits for the data sampled by the ADC. When the ADC sampling process is completed, it enters the ADC interrupt response function. In this function, the data reading is mainly completed. For small signals, the amplitude is amplified by the programmable amplifier and then stored in the custom buffer area. The two serial port working modes are all sent by the host computer to trigger the serial port receiving interrupt service function of the SCI. Then the corresponding command requirements are completed in the interrupt service function. The system selects serial port 1 to complete the transmission of the collected data to the host computer, and serial port 0 to complete the sending of the data to be saved and some related operations to the EEPROM. SCI0 and SCI1 correspond to INT9.1 and INT9.3 of the DSC peripheral interrupt respectively, and the external interrupt XINT1 corresponds to INT1.4. The program sets the transmission rate of the two serial ports to 38.4 kb·s-1.

　　When the device is working, since the interrupt source of SCI1 is the command sent by the host computer, the system stipulates that the host computer sends a data acceptance command every 20ms, so the interrupt response period of SCI1 is td = 20 ms. Since the sampling rate is 40 kHz, the interrupt service function response period of ADC is 0.025 ms. The system stipulates that the number of data collected is 50, so the time to collect a group of data is tc = 1.25 ms, so in one SCI1 interrupt process, ADC will collect 16 groups of data. Considering that the baud rate of serial port transmission is 38.4kb·s-1, the time to transmit a 16-bit data is tt = 0.417 ms. The time to collect a group of data plus the time to transmit serial port data is tc + tt = 1.667 ms. 4 Conclusion

　　The designed signal processing board uses TMS320F28335 as the core processor and AD7656 to complete the functional hardware platform of analog signal sampling. TMS320F28335 integrates rich peripheral resources. Through the configuration of driver software and the design of hardware system, it can conveniently and efficiently complete the processing and operation of a large number of digital signals. AD7656's 6-channel analog signal acquisition and 16-bit high-precision analog signal sampling can better complete the digital conversion of analog signals and reduce the distortion of analog signal sampling. Experiments show that the error value of the digital signal collected by the signal processing board is about 1.37 mV, which can reach 14-bit sampling accuracy.